A Hardware/Software Co-Design Flow for Dynamic Partial Reconfiguration

2012 ◽  
Vol 433-440 ◽  
pp. 5172-5177
Author(s):  
Xiao Jing Feng ◽  
Xi Li ◽  
Wang Chao ◽  
Xue Hai Zhou ◽  
Jun Neng Zhang
Keyword(s):  
Embedded Systems ◽  
Hardware Design ◽  
Design Flow ◽  
Experimental Results ◽  
Prototype System ◽  
Partial Reconfiguration ◽  
Dynamic Partial Reconfiguration ◽  
Software And Hardware ◽  
Reconfiguration Overhead ◽  
Hardware Designs

The strict requirements on both performance and flexibility lead us to apply Dynamic Partial Reconfiguration (DPR) technology in embedded systems. However, existing DPR design flows are still immature, since previous works mainly focus on hardware designs while ignore software designs for DPR. To remedy this weakness, this paper proposes a hardware/software (HW/SW) co-design flow for DPR. The co-design flow aims at accelerating the process of DPR designs, and it merges software and hardware design flows to make them operate in parallel. Besides, in order to validate the effectiveness of our co-design flow, we implement a partial self-reconfigurable prototype system on Xilinx Virtex-5 platform and perform a set of experiments. Experimental results present that the reconfiguration overhead for partial reconfiguration is only 4.66% against global reconfiguration in our prototype. It’s also presented that our prototype can achieve a 23.6 × speedup over software algorithm solutions.

Dynamic Reconfiguration for Internal Monitoring Services

2016 ◽  
pp. 124-136
Author(s):  
Julio Daniel Dondo Gazzano ◽  
Fernando Rincon Calle ◽  
Julian Caba ◽  
David de la Fuente ◽  
Jesus Barba Romero
Keyword(s):  
Quality Assurance ◽  
Monitoring System ◽  
Hardware Design ◽  
Dynamic Reconfiguration ◽  
Design Flow ◽  
Added Value ◽  
Partial Reconfiguration ◽  
Dynamically Reconfigurable ◽  
Simulation Process ◽  
Hardware Component

In hardware design flow, testing is the most important step to hardware quality assurance before a hardware component is released. However simulation and verification during design steps are not enough to guarantee a system without failures. In many cases the system fails after have been deployed. Dynamically reconfigurable FPGAs have the ability to reconfigure part of its architecture during run time without stopping the whole system. This feature is an added value that can be exploited for internal system monitoring and verification. Using partial reconfiguration, an Internal Monitoring System can be implemented in reconfigurable areas for monitoring different conditions and signals in the circuit, after implementation. This allows detecting and identifying those failures that were not possible to detect during simulation process.

A dynamic partial reconfiguration design flow for permanent faults mitigation in FPGAs

2018 ◽  
Vol 83 ◽  
pp. 50-63 ◽  
Author(s):  
Victor Manuel Gonçalves Martins ◽  
Paulo Ricardo Cechelero Villa ◽  
Rodrigo Travessini ◽  
Marcelo Daniel Berejuck ◽  
Eduardo Augusto Bezerra
Keyword(s):  
Design Flow ◽  
Partial Reconfiguration ◽  
Dynamic Partial Reconfiguration ◽  
Permanent Faults

High-level design flow and environment for FPGA-based dynamic partial reconfiguration

2017 ◽  
Vol 104 (8) ◽  
pp. 1254-1284
Author(s):  
Abdessalem Ben Abdelali ◽  
Marwa Hannachi ◽  
Mohamed Nidhal Krifa ◽  
Hassan Rabah ◽  
Abdellatif Mtibaa
Keyword(s):  
Design Flow ◽  
Partial Reconfiguration ◽  
Dynamic Partial Reconfiguration ◽  
Level Design ◽  
High Level

Compiler-Aided Run-Time Performance Speed-Up in Super-Scalar Processor

10.28945/3391 ◽  
2009 ◽  
Author(s):  
Moshe Pelleh
Keyword(s):  
Embedded Systems ◽  
Embedded System ◽  
General Purpose ◽  
Experimental Results ◽  
Medium Size ◽  
Organic System ◽  
Software Application ◽  
Organic Systems ◽  
Special Cases ◽  
Run Time

In our world, where most systems become embedded systems, the approach of designing embedded systems is still frequently similar to the approach of designing organic systems (or not embedded systems). An organic system, like a personal computer or a work station, must be able to run any task submitted to it at any time (with certain constrains depending on the machine). Consequently, it must have a sophisticated general purpose Operating System (OS) to schedule, dispatch, maintain and monitor the tasks and assist them in special cases (particularly communication and synchronization between them and with external devices). These OSs require an overhead on the memory, on the cache and on the run time. Moreover, generally they are task oriented rather than machine oriented; therefore the processor's throughput is penalized. On the other hand, an embedded system, like an Anti-lock Braking System (ABS), executes always the same software application. Frequently it is a small or medium size system, or made up of several such systems. Many small or medium size embedded systems, with limited number of tasks, can be scheduled by our proposed hardware architecture, based on the Motorola 500MHz MPC7410 processor, enhancing its throughput and avoiding the software OS overhead, complexity, maintenance and price. Encouraged by our experimental results, we shall develop a compiler to assist our method. In the meantime we will present here our proposal and the experimental results.

Sign in / Sign up

Export Citation Format

Share Document