Hardware Acceleration of CBIR System with FPGA-Based Platform

Typical applications involving image retrieval processes demand a great amount of computation. The visual content of the images is extracted and represented by means of descriptor vectors of multidimensional characteristics. The image retrieval process consists of two tasks: (1) generation of database and indexing; and (2) the search process. The first task involves the construction of descriptor vectors. Then, an index is built upon the database to speed the search process. The second requires calculating a descriptor vector for the query image and computes the similarity search with the ones stored in the index. In this context, it is relevant to devise new algorithms and different parallel platforms that can reduce execution times. In particular, this work focuses on platforms with FPGAs based SoCs to present and evaluate a two stage system where the index is constructed off-line and the similarity search is executed on-line. Results show that the FPGA is 73% faster than a 2 Quad CPU to compute the descriptor vector of an image when using the Color Layout Descriptor of MPEG-7.

Reconfigurable Virtual Instrumentation Based on FPGA for Science and High-Education

In this chapter we will show how modern FPGA offers the possibility of implementing Reconfigurable Virtual Instrumentation, a new kind of electronic instrumentation which generates interesting opportunities for regular users but that also poses several technical challenges for advanced users and instrument developers. We will analyze some of the main problems and we will give some ideas and possible strategies to deal with them. In order to put the subject in the right context we will review some general concepts regarding instrumentation in general and we later proceed with some more specific concepts and definitions. The chapter also describes two hardware/software platforms for science and high-education developed at the International Centre for Theoretical Physics (ICTP) where the concept of RVI proposed in this chapter was applied. Although we mainly adopt a scientist's prospective to define and analyze instrumentation, most of the conclusions drawn along this chapter can be easily generalized for a wide range of applications in commercial or industrial sectors.

Hardware Implementation of a Genetic Algorithm for Motion Path Planning

The aim of this chapter is to investigate the hardware (H/W) implementation of Genetic Algorithm (GA) based motion path planning of robot. The potential benefit of using H/W implementation of genetic algorithm is that it allows the use of huge parallelism which is suited to random number generation, crossover, mutation and fitness evaluation. The operation of selection and reproduction are basically problem independent and involve basic string manipulation tasks. The fitness evaluation task, which is problem dependent, however proves a major difficulty in H/W implementation. Another difficulty comes from that designs can only be used for the individual problem their fitness function represents. Therefore, in this work the genetic operators are implemented in H/W, while the fitness evaluation module is implemented in software (S/W). This allows a mixed hardware/software approach to address both generality and acceleration. Moreover, a simple H/W implementation for fitness evaluation of robot motion path planning problem is discussed.

Optimization of Advanced Signal Processing Architectures for Detection of Signals Immersed in Noise

The use of Field Programmable Gate Array (FPGA) devices in the signal processing field has been on a constant rise since the beginning of the last decade. In particular, in the field of signal processing applications, the implementation of methods and techniques for the detection of coded signals immersed in noise should be highlighted. In this chapter, focus is placed on a special type of coding known as Complementary Sequences, and on some of the coding schemes derived from them. These sequences have been employed in many different application fields, ranging from safety sensors and radar systems to communications and material characterization. Specifically, this chapter deals with issues related to algorithms improvement and to their implementation in FPGA platforms, with particular emphasis on hardware resources efficiency and on the reliability of the whole processing scheme.

Implementation of a Smart Sensor Node for Wireless Sensor Network Applications Using FPGAs

Applications that involve monitoring of environmental parameters require measuring devices to be placed at different geographical locations but are controlled centrally at a remote site. The measuring devices in such applications need to be physically small, consume low power, and must be capable of local processing tasks facilitating the mobility to span the measuring area in a vast geographic area. This chapter presents the design of a generalized, re-configurable, re-programmable smart sensor node using a Zigbee with a Field-Programmable Gate Array (FPGA) that embeds all processing and communication functionalities based on the IEEE 1451 family of standards. Design of the sensor nodes includes communication, processing and transducer control functionalities in a single core increasing the speedup of processing power due to inter-process communication taking place within the chip itself.

Dynamic Reconfiguration for Internal Monitoring Services

In hardware design flow, testing is the most important step to hardware quality assurance before a hardware component is released. However simulation and verification during design steps are not enough to guarantee a system without failures. In many cases the system fails after have been deployed. Dynamically reconfigurable FPGAs have the ability to reconfigure part of its architecture during run time without stopping the whole system. This feature is an added value that can be exploited for internal system monitoring and verification. Using partial reconfiguration, an Internal Monitoring System can be implemented in reconfigurable areas for monitoring different conditions and signals in the circuit, after implementation. This allows detecting and identifying those failures that were not possible to detect during simulation process.

FPGA Implementations for Chaotic Maps Using Fixed-Point and Floating-Point Representations

This work presents the implementation of various chaotic maps; among the maps there are one-dimensional and two-dimensional ones. In order to implement the maps, their mathematical descriptions are modified to be represented with more accuracy by different binary representations. The sequences from the same map are compared to determine until which iteration, different descriptions produce similar outputs. The similarity coefficient is established in five percent. Comparison delivers some interesting findings; first, the one-dimensional maps, in this work, have comparative number of similar iterations. Second, the bi-dimensional maps present the lowest and highest number of similar iterations. Based on the modified mathematical descriptions, the VHDL implementations are developed. They are simulated and their results are compared against the modified mathematical description ones; resulting that both groups of results are congruent.

Methodology for FPGA Implementation of a Chaos-Based AWGN Generator

Additive White Gaussian Noise (AWGN) generators are a basic tool for the test and measurement of digital systems. One drawback for hardware implementation of the classically used algorithms is that they require the hardware implementation of complex operations (such as sinusoidal and logarithmic functions). In this chapter, a method for the design and hardware implementation of an AWGN generator based on chaotic maps is described. The advantage is that deterministic chaotic systems are described by simple nonlinear equations, and therefore, they are straightforward to implement in hardware. To ensure that the generated sequence has the desired Probability Density Function (PDF), the chaotic map, which is the heart of the system, is synthesized using an approach based on the theory of positive matrices method. The hardware implementation was developed using an Altera Cyclone III FPGA with the 3C120 Development Board.

Development of Algorithms and Their Hardware Implementation for Gamma Radiation Spectrometry

The chapter describes how to develop algorithms for Gamma ray spectrometry portable instruments and then to implement them on FPGA devices as hardware platform. At first we consider the development of more accurate spectrum evaluation programs including pileup detection and recovery, dead time correction, coincidence summing and resolution enhancement algorithms which are implemented in MATLAB. The input signals are obtained through experimental setup or simulated model. Four different approaches are studied and evaluated for peak pileup problem within a spectroscopy system. In addition, x-ray spectrum evaluation enhancements are carried out and several algorithms are developed and compared. Hardware implementation using Xilinx DSP Boards as well as further improvements and modifications are discussed.

Implementation of Reactor Control Rod Position Sensing/Display Using a VLSI Chip

The chapter describes the use of CPLDs and FPGAs devices in Nuclear Power Plant (NPP) Instruments. The design, simulation, implementation and test of a reactor control rod position sensing electronic unit intended as a replacement of the outdated Russian type in old power reactors is presented. The signals are generated from12 ring-shaped pair of inductively coupled coils surrounding the reactor moving rod. The implementation involves both analog and digital design. The designed digital circuit has 12 TTL outputs working in a 1-out-of-12 mode, excluding both double [2-out-of-12] and no-output state. To avoid a flickering display during transition between two neighboring positions, some sort of hysteresis is implemented. One time this hysteresis is implemented through a state machine deriving up/down counter. The state machine is synthesized targeting a Xilinx Spartan XL device. To reduce the possibility of power failure effects, another circuit consists of combinatorial logic and implemented in CPLD is presented. However, energy harvesting methods in NPPs can support counter based design.