Study on the Addressing Mode of Assembly Language Instruction Set of 80C51 MCU

2012 ◽  
Vol 591-593 ◽  
pp. 1511-1514
Author(s):  
Bao Fa Sun
Keyword(s):  
Assembly Language ◽  
Language Instruction ◽  
Instruction Set ◽  
Base Address

The addressing mode of assembly language instruction set of 80C51 MCU is redefined. The addressing mode is classified according to two standards separately. The addressing mode is the method decrypting operand address in the instruction, or finding the next instruction address. The mode to find the operand address includes direct addressing, register addressing, register indirect addressing and base address plus index indirect addressing. The mode to find the next instruction address includes sequential addressing, base address plus index indirect addressing and relative addressing.

scholarly journals An Optimization Framework for Codes Classification and Performance Evaluation of RISC Microprocessors

Symmetry ◽  
2019 ◽  
Vol 11 (7) ◽  
pp. 938
Author(s):  
Syed Rameez Naqvi ◽  
Ali Roman ◽  
Tallha Akram ◽  
Majed M. Alhaisoni ◽  
Muhammad Naeem ◽  
...  
Keyword(s):  
Assembly Language ◽  
Optimization Method ◽  
Instruction Set ◽  
Mathematical Performance ◽  
Optimization Framework ◽  
And Performance ◽  
Reduced Instruction Set Computer ◽  
High Level ◽  
The Given ◽  
Primary Contribution

Pipelines, in Reduced Instruction Set Computer (RISC) microprocessors, are expected to provide increased throughputs in most cases. However, there are a few instructions, and therefore entire assembly language codes, that execute faster and hazard-free without pipelines. It is usual for the compilers to generate codes from high level description that are more suitable for the underlying hardware to maintain symmetry with respect to performance; this, however, is not always guaranteed. Therefore, instead of trying to optimize the description to suit the processor design, we try to determine the more suitable processor variant for the given code during compile time, and dynamically reconfigure the system accordingly. In doing so, however, we first need to classify each code according to its suitability to a different processor variant. The latter, in turn, gives us confidence in performance symmetry against various types of codes—this is the primary contribution of the proposed work. We first develop mathematical performance models of three conventional microprocessor designs, and propose a symmetry-improving nonlinear optimization method to achieve code-to-design mapping. Our analysis is based on four different architectures and 324,000 different assembly language codes, each with between 10 and 1000 instructions with different percentages of commonly seen instruction types. Our results suggest that in the sub-micron era, where execution time of each instruction is merely in a few nanoseconds, codes accumulating as low as 5% (or above) hazard causing instructions execute more swiftly on processors without pipelines.

scholarly journals Machine-Code Program Evolution by Genetic Programming Using Asynchronous Reference-Based Evaluation Through Single-Event Upset in On-Board Computer

2017 ◽  
Vol 29 (5) ◽  
pp. 808-818
Author(s):  
Tomohiro Harada ◽  
Keiki Takadama ◽  
◽  
Keyword(s):  
Genetic Programming ◽  
Assembly Language ◽  
Occurrence Rate ◽  
Instruction Set ◽  
Single Event ◽  
Threshold Selection ◽  
Simulation Experiments ◽  
Language Program ◽  
Single Event Upsets ◽  
Correct Program

This study proposes a novel genetic programming method using asynchronous reference-based evaluation (called AREGP) to evolve computer programs through single-event upsets (SEUs) in the on-board computer in space missions. AREGP is an extension of Tierra-based asynchronous genetic programming (TAGP), which was proposed in our previous study. It is based on the idea of the biological simulator, Tierra, where digital creatures are evolved through bit inversions in a program. AREGP not only inherits the advantages of TAGP but also overcomes its limitation, i.e., TAGP cannot select good programs for evolution without an appropriate threshold. Specifically, AREGP introduces an archive mechanism to maintain good programs and a reference-based evaluation by using the archive for appropriate threshold selection and removal. To investigate the effectiveness of the proposed AREGP, simulation experiments are performed to evolve the assembly language program in the SEU environment. In these experiments, the PIC instruction set, which is carried on many types of spacecraft, is used as the evolved assembly program. The experimental results revealed that AREGP cannot only maintain the correct program through SEU with high occurrence rate, but is also better at reducing the size of programs in comparison with TAGP. Additionally, AREGP can achieve a shorter execution step and smaller size of programs, which cannot be achieved by TAGP.

Digital Processing of STEM Images

1981 ◽  
Vol 39 ◽  
pp. 236-237
Author(s):  
A. V. Crewe ◽  
M. Ohtsuki
Keyword(s):  
High Resolution ◽  
Low Dose ◽  
Assembly Language ◽  
Processing System ◽  
Principal Component ◽  
Digital Processing ◽  
Image Analysis System ◽  
Black And White ◽  
Analysis System ◽  
Dose Imaging

We have assembled an image processing system for use with our high resolution STEM for the particular purpose of working with low dose images of biological specimens. The system is quite flexible, however, and can be used for a wide variety of images.The original images are stored on magnetic tape at the microscope using the digitized signals from the detectors. For low dose imaging, these are “first scan” exposures using an automatic montage system. One Nova minicomputer and one tape drive are dedicated to this task.The principal component of the image analysis system is a Lexidata 3400 frame store memory. This memory is arranged in a 640 x 512 x 16 bit configuration. Images are displayed simultaneously on two high resolution monitors, one color and one black and white. Interaction with the memory is obtained using a Nova 4 (32K) computer and a trackball and switch unit provided by Lexidata.The language used is BASIC and uses a variety of assembly language Calls, some provided by Lexidata, but the majority written by students (D. Kopf and N. Townes).

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