Dual-Edge Triggered T Flip-Flop Structure Using Quantum-Dot Cellular Automata

2013 ◽  
Vol 662 ◽  
pp. 562-567 ◽  
Author(s):  
Lin Rong Xiao ◽  
Xiang Xu ◽  
Shi Yan Ying
Keyword(s):  
Cellular Automata ◽  
Quantum Dot ◽  
Circuit Design ◽  
High Performance ◽  
Clock Frequency ◽  
Single Edge ◽  
Sequential Circuit ◽  
Flip Flop ◽  
Quantum Dot Cellular Automata ◽  
Combinational Logic Circuits

As an emerging nanotechnology, quantum-dot cellular automata (QCA) has the potential to be used for next generation VLSI. Various designs of combinational logic circuits have been proposed for QCA implementation, but sequential circuit design is limited due to the lack of high-performance QCA flip-flops. After an introduction on QCA and dual-edge triggered (DET) flip-flops, a new QCA DET T flip-flop following a pulsed latch scheme is presented. The proposed T flip-flop is simulated using QCADesigner simulator and its logic functionality is verified. The same data throughput of the DET flip-flop can be achieved while operating at half the clock frequency of a single-edge triggered (SET) counterpart. The proposed flip-flop is promising in building QCA sequential circuits with low power and high performance.

Towards the Design of Cost-efficient Generic Register Using Quantum-dot Cellular Automata

2020 ◽  
Vol 10 (4) ◽  
pp. 534-547
Author(s):  
Chiradeep Mukherjee ◽  
Saradindu Panda ◽  
Asish K. Mukhopadhyay ◽  
Bansibadan Maji
Keyword(s):  
Cellular Automata ◽  
Quantum Dot ◽  
Power Dissipation ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Digital Data ◽  
Design Parameters ◽  
Flip Flop ◽  
Quantum Dot Cellular Automata ◽  
Cost Efficient

Background: The advancement of VLSI in the application of emerging nanotechnology explores quantum-dot cellular automata (QCA) which has got wide acceptance owing to its ultra-high operating speed, extremely low power dissipation with a considerable reduction in feature size. The QCA architectures are emerging as a potential alternative to the conventional complementary metal oxide semiconductor (CMOS) technology. Experimental: Since the register unit has a crucial role in digital data transfer between the electronic devices, such study leading to the design of cost-efficient and highly reliable QCA register is expected to be a prudent area of research. A thorough survey on the existing literature shows that the generic models of Serial-in Serial Out (SISO), Serial-in-Parallel-Out (SIPO), Parallel-In- Serial-Out (PISO) and Parallel-in-Parallel-Out (PIPO) registers are inadequate in terms of design parameters like effective area, delay, O-Cost, Costα, etc. Results: This work introduces a layered T gate for the design of the D flip flop (LTD unit), which can be broadly used in SISO, SIPO, PISO, and PIPO register designs. For detection and reporting of high susceptible errors and defects at the nanoscale, the reliability and defect tolerant analysis of LTD unit are also carried out in this work. The QCA design metrics for the general register layouts using LTD unit is modeled. Conclusion: Moreover, the cost metrics for the proposed LTD layouts are thoroughly studied to check the functional complexity, fabrication difficulty and irreversible power dissipation of QCA register layouts.

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