Design Optimization of 1.2kV 4H-SiC Trench MOSFET
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In a trench MOSFET structure, p+ trench bottom implant (also called p+ shielding region) is commonly used to protect the gate oxide from high electric field stress, however, if the design and fabrication process are not optimized properly, the p+ shielding region together with n-drift and the p-base region will form a parasitic JFET which severely degrades the on-state performance of the device. This paper presents this parasitic JFET effect with experimental results and the optimization work that has been done to eliminate the parasitic JFET.
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2007 ◽
Vol 353
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pp. 170-179
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2011 ◽
Vol 26
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pp. 085019
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2011 ◽
Vol 158
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pp. R27
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2012 ◽
Vol 12
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pp. 94-100
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1992 ◽
Vol 83-87
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pp. 1427-1432
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