Analysis of SRAM bit cell topologies in submicron CMOS technology

International Journal of Simulation Systems Science & Technology ◽

10.5013/ijssst.a.16.06.13 ◽

2020 ◽

Author(s):

Vipul Bhatnagar ◽

Pradeep Kumar ◽

Sujata Pandey

Keyword(s):

Cmos Technology ◽

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Equivalent circuit models for stacked spiral inductors in deep submicron CMOS technology

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03. ◽

10.1109/iscas.2003.1205682 ◽

2003 ◽

Author(s):

S.C. Rustagi ◽

Chun-Geik Tan

Keyword(s):

Equivalent Circuit ◽

Cmos Technology ◽

Deep Submicron ◽

Spiral Inductors ◽

Submicron Cmos ◽

Equivalent Circuit Models

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Process and device considerations for micron and submicron CMOS technology

10.1109/iedm.1985.190985 ◽

1985 ◽

Author(s):

L.C. Parrillo

Keyword(s):

Cmos Technology ◽

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Noise and speed characteristics of test transistors and charge amplifiers designed using a submicron CMOS technology

Nuclear Instruments and Methods in Physics Research Section A Accelerators Spectrometers Detectors and Associated Equipment ◽

10.1016/s0168-9002(96)00356-7 ◽

1996 ◽

Vol 380 (1-2) ◽

pp. 350-352 ◽

Author(s):

J.C Santiard ◽

F Faccio

Keyword(s):

Cmos Technology ◽

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Lateral SCR devices with low-voltage high-current triggering characteristics for output ESD protection in submicron CMOS technology

IEEE Transactions on Electron Devices ◽

10.1109/16.662790 ◽

1998 ◽

Vol 45 (4) ◽

pp. 849-860 ◽

Author(s):

Ming-Dou Ker

Keyword(s):

Low Voltage ◽

Cmos Technology ◽

High Current ◽

Esd Protection ◽

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Study of SRAM Standby Leakage Reduction Techniques for Deep-submicron CMOS Technology

International Journal of Control and Automation ◽

10.14257/ijca.2017.10.10.05 ◽

2017 ◽

Vol 10 (10) ◽

pp. 49-62

Author(s):

Satyendra Kumar ◽

Kaushik Saha ◽

Hariom Gupta

Keyword(s):

Cmos Technology ◽

Deep Submicron ◽

Leakage Reduction ◽

Reduction Techniques ◽

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Field Isolation Using Shallow Trenches for Submicron CMOS Technology

ESSDERC ’89 ◽

10.1007/978-3-642-52314-4_29 ◽

1989 ◽

pp. 147-150

Author(s):

G. Zwicker ◽

P. Lange ◽

P. Staudt-Fischbach ◽

W. Windbracke

Keyword(s):

Cmos Technology ◽

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Combination of LOCOS and BOX Isolation for Submicron CMOS Technology

ESSDERC ’89 ◽

10.1007/978-3-642-52314-4_26 ◽

1989 ◽

pp. 135-138 ◽

Author(s):

Ch. Zeller ◽

F. X. Stelz

Keyword(s):

Cmos Technology ◽

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Upset hardened memory design for submicron CMOS technology

IEEE Transactions on Nuclear Science ◽

10.1109/23.556880 ◽

1996 ◽

Vol 43 (6) ◽

pp. 2874-2878 ◽

Author(s):

T. Calin ◽

M. Nicolaidis ◽

R. Velazco

Keyword(s):

Cmos Technology ◽

Memory Design ◽

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Hot carrier reliability improvement by utilizing phosphorus transient enhanced diffusion for input/output devices of deep submicron CMOS technology

IEEE Electron Device Letters ◽

10.1109/55.887478 ◽

2000 ◽

Vol 21 (12) ◽

pp. 598-600 ◽

Author(s):

H.H.-C. Wang ◽

C.H. Diaz ◽

Boon-Khim Liew ◽

J.Y.-C. Sun ◽

Tahui Wang

Keyword(s):

Cmos Technology ◽

Deep Submicron ◽

Input Output ◽

Hot Carrier ◽

Enhanced Diffusion ◽

Reliability Improvement ◽

Transient Enhanced Diffusion ◽

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MONOLITHIC SENSORS IN DEEP SUBMICRON CMOS TECHNOLOGY FOR LOW MATERIAL BUDGET, HIGH RATE HEP APPLICATIONS

Astroparticle, Particle and Space Physics, Detectors and Medical Physics Applications ◽

10.1142/9789812819093_0003 ◽

2008 ◽

Author(s):

C. ANDREOLI ◽

L. RATTI ◽

M. MANGHISONI ◽

G. TRAVERSI

Keyword(s):

Cmos Technology ◽

Deep Submicron ◽

High Rate ◽

Submicron Cmos ◽

Material Budget

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