scholarly journals An Efficient VLSI Architecture for FIR Filter using Computation Sharing Multiplier

2012 ◽  
Vol 54 (14) ◽  
pp. 1-6
Author(s):  
Thamizharasan .V ◽  
Parthipan.V Parthipan.V
Keyword(s):  
Vlsi Architecture ◽  
Fir Filter ◽  
Computation Sharing

scholarly journals A NOVEL VLSI ARCHITECTURE OF HIGH SPEED 1D DISCRETE WAVELET TRANSFORM

2015 ◽  
pp. 160-166
Author(s):  
POOJA GUPTA ◽  
Saroj Kumar Lenka
Keyword(s):  
High Speed ◽  
Performance Metrics ◽  
Critical Path ◽  
Vlsi Architecture ◽  
Fir Filter ◽  
Optimization Techniques ◽  
Discrete Wavelet ◽  
Path Delay ◽  
Linear Phase ◽  
Data Interleaving

This paper describes an efficient implementation for a multi-level convolution based 1-D DWT hardware architecture for use in FPGAs. The proposed architecture combines some hardware optimization techniques to develop a novel DWT architecture that has high performance and is suitable for portable and high speed devices. The first step towards the hardware implementation of the DWT algorithm was to choose the type of FIR filter block. Firstly we design the high speed linear phase FIR filter using pipelined and parallel arithmetic methods. This proposed filter employs efficiently distributed D-latches and multipliers. Furthermore this filter is used in the proposed DWT architecture. Thus, the new VLSI architecture based on combining of fast FIR filters for reducing the critical path delay and data interleaving technique for lower chip area. We synthesized the final design using Xilinx 9.1i ISE tool. We illustrate that a DWT design using a pipelined linear phase FIR filter coupled with data-interleaving gives the best combination of the performance metrics when compared to other DWT structures.

scholarly journals Design and Implementation of FIR Filter using Efficient MAC

2020 ◽  
Vol 9 (3) ◽  
pp. 878-881
Keyword(s):  
Finite Impulse Response ◽  
Optimization Technique ◽  
Vlsi Architecture ◽  
Building Blocks ◽  
Fir Filter ◽  
Total Power ◽  
Area Efficiency ◽  
Logic Optimization ◽  
Gate Count ◽  
Impulse Response Filter

The Design And Realization Of Efficient Multiplication And Accumulation Unit (MAC) Of A Digital FIR Filter Has Substantial Influence In Designing A Well-Organized Finite Impulse Response Filter As It Is Used To Compute The Filter Response. Area Efficiency In An FIR Filter Can Be Achieved By Reducing The Gate Count Of Either Multiplier Unit Or An Adder Unit Or Both The Units Since They Are The Basic Building Blocks Of FIR Filter. This Paper Presents A VLSI Architecture For A 4-Tap FIR Filter Which Is Designed By Using Efficient Adder And A Multiplier Employing Logic Optimization Technique. Area For MAC Based FIR Filter Employing Vedic-CSLALOT Is Improved By 11.959% When Compared To Hierarchy-SQRT-CSLA. Total Power For MAC Based FIR Filter Employing Vedic-CSLALOT Is Improved By 13.15% As Against To Hierarchy-SQRT-CSLA.

Computation Sharing Programmable FIR Filter for Low-Power and High-Performance Applications

2004 ◽  
Vol 39 (2) ◽  
pp. 348-357 ◽  
Author(s):  
J. Park ◽  
W. Jeong ◽  
H. Mahmoodi-Meimand ◽  
Y. Wang ◽  
H. Choo ◽  
...  
Keyword(s):  
Low Power ◽  
High Performance ◽  
Fir Filter ◽  
Computation Sharing

scholarly journals CSHM Multiplier and Radix-256 Algorithm using Fir Filter Design

2019 ◽  
Vol 8 (11S) ◽  
pp. 822-825
Keyword(s):  
Filter Design ◽  
Finite Impulse Response ◽  
Fir Filter ◽  
Partial Product ◽  
Unit Of Measurement ◽  
Element Addition ◽  
Fir Filter Design ◽  
Impulse Response Filter ◽  
Computation Sharing ◽  
Free Element

The Rredundant Binary (RB) systems are wellliked for the reason that of its distinctive carry broadcast free addition. Thus a specific filter called as Finite Impulse Response filter computes its yield exploitation multiply& accumulation process. At intervals the reward work, a FIR filter supported to new higher radix-256 and chemical element arithmetic is implemented. The employment of radix-256 booth secret writing cut down the amount of partial product rows in any multiplication by eight fold. Present work inputs and coefficients unit of measurement thought-about of 16-bit. Hence, entirely two partial product rows unit of quantity obtained in Redundant Binary (RB) kind for both input and constant multiplications. These two partial product rows unit of measurement added exploitation carry free element addition. The final output is converted back to Natural Binary (NB). The planned number technique for FIR filter is compared with Computation Sharing Multiplier (CSHM) implementation.

A Crystal View on the Design of FIR Filter

2020 ◽  
Vol 17 (9) ◽  
pp. 4235-4238
Author(s):  
R. Rohini ◽  
N. V. Satya Narayana ◽  
Durgesh Nandan
Keyword(s):  
High Speed ◽  
Critical Path ◽  
Sampling Rate ◽  
Vlsi Architecture ◽  
Complete Information ◽  
Low Complexity ◽  
Fir Filter ◽  
Main Element ◽  
Fir Filters ◽  
Hybrid Form

In audio and video signal processing main element is the FIR filter. This paper presents complete information regarding the FIR filters. It also focuses on the design of FIR filters which provide low-area, energy-delay, low-power consumption, high-speed, low critical path, and low complexity. Implementation of FIR filters with different methods like memory-based VLSI architecture, filters for sampling rate conversion, linear phase FIR filters, optimal hybrid form FIR filters, Nyquist filters, hybrid multiplier less FIR filters, low complexity FIR filters, variable partition hybrid form FIR filters, area efficiency FIR filters are discussed in this paper. The objective of this paper to provide all related information regarding FIR filters at one platform.

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