Segmentation of Database Images Using Gradient Based Multiscale Morphological Reconstruction

The main purpose of this research is to improve the accuracy of object segmentation in database images by constructing an object segmentation algorithm. Image segmentation is a crucial step in the field of image processing and pattern recognition. Segmentation allows the identification of structures in an image which can be utilized for further processing. Both region-based and object-based segmentation are utilized for large-scale database images in a robust and principled manner. Gradient based MultiScalE Graylevel mOrphological recoNstructions (G-SEGON) is used for segmenting an image. SEGON roughly identifies the background and object regions in the image. This proposed method comprises of four phases namely pre-processing phase, object identification phase, object region segmentation phase, majority selection and refinement phase. After developing the grey level mesh the resultant image is converted into gradient and K-means clustering segmentation algorithm is used to segment the object from the gradient image. After implementation the accuracy of the proposed G-SEGON technique is compared with the existing method to prove its efficiency.

IMPLEMENTATION OF HIGH SPEED-LOW POWER TRUNCATION ERROR TOLERANT ADDER

Now a Days in modern VLSI technology different kinds of errors are invitable. A new type of adder i.e. error tolerant adder(ETA) is proposed to tolerate those errors and to attain low power consumption and high speed performance in DSP systems. In conventional adder circuit, delay is mainly certified to the carry propagation chain along the critical path, from the LSB to MSB. If the carry propagation can be eliminated by the technique proposed in this paper, a great improvement in speed performance and power consumption is achieved. By operating shifting and addition in parallel, the error tolerant adder tree compensates for the truncation errors. To prove the feasibility of the ETA, normal addition operation present in the DFT or DCT algorithm is replaced by the proposed addition arithmetic and the experimental results are shown. In this paper we propose error tolerant Adder (ETA). In the view of DSP applications the ETA is able to case the strict restriction on accuracy, speed performance and power consumption when compared to the conventional Adders, the proposed one provides 76% improvement in power-delay product such a ETA plays a key role in digital signal processing system that can tolerate certain amount of errors.

3D TARGET DETECTION USING STACKED HOLOGRAM

A very popular technique of 3D vision now-a-days is holography which has many advantages over the stereoscopic 3D vision. The same technique can be implemented on RADAR to take high resolution 3D picture of the target and to track with very minute displacement. As this does not employ parallax method, so binocular antenna can be replaced by a single antenna. Again in this thesis another new concept, gated range, is implemented, i.e., the target can be detected within a certain range on spatial domain so that it can focus to the target and the clutter has no effect on it. Narrow virtual transmit pulses are synthesized by differencing long-duration, staggered pulse repetition interval (PRI) transmit pulses. PRI is staggered at an intermediate frequency IF. Echoes from virtual pulses form IF-modulated interference patterns with a reference wave. Samples of interference patterns are IF-filtered to produce high spatial resolution holographic data. PRI stagger can be very small, e.g., 1-ns, to produce a 1-ns virtual pulse from very long, staggered transmit pulses. Occupied Bandwidth (OBW) can be less than 10 MHz due to long RF pulses needed for holography, while spatial resolution can be very high, corresponding to ul tra-wideband (UWB) operation, due to short virtual pulses. X-Y antenna scanning can produce range-gated surface holograms from quadrature data. Multiple range gates can produce stacked-in-range holograms. Motion and vibration can be detected by changes in interference patterns within a range-gated zone.

Reliability Analysis of A Radial Distributed Generation Distribution System

Distributed Generation (DG) plays an important role in current power systems with high demand growth. DG provides an alternative to the traditional electricity sources like oil, gas, coal, water, etc. and can also be used to enhance the current electrical system. DG distribution is likely to improve the reliability of a power distribution system by at least partially minimizing unplanned power interruptions to customers due to loss of utility generators or due to faults in transmission and distribution lines/equipments. In this paper, a typical distribution system is considered and to show the reliability enhancement of the system, different components (fuses, disconnects, DGs) are step by step taken into account and added to the system in five cases. Analytical methodology is used for the analysis. The results demonstrate that DG does improve the reliability of the distribution system.

SPEED CONTROL OF INDUCTION MOTOR USING ADR CONTROLLER

The control of induction motors has been a primary concern of researchers. Proportional-integral- derivative (PID) control and direct torque control (DTC) have been proposed for induction motors [1-6]. However, the control of induction motors is still a challenging problem due to the following issues: 1) the dynamic system of an induction motor is highly nonlinear; 2) the rotor resistance varies because of heating. In this paper, a reduced-order active disturbance rejection control (ADRC) with reduced order extended state observer (RESO) is applied for induction motor control. The ADRC is employed for controlling a slip.

POWER REDUCTION BY GUARDED EVALUATION CONSIDERING LOGIC ARCHITECTURE AND USING CLOCK GATING

In this paper, guarded evaluation is a dynamic power reduction technique by identifying sub circuits inputs and kept constant at specific times during circuit operation. In certain condition, some signals within the digital design are not observable at output. So make such signals as guarded (constant). There by reducing the dynamic power. Here we apply this technique for all digital circuits. The problem here is to find conditions under which a sub circuit input can be held constant with disturbing the main circuit functionally (correctness). Here we propose a solution for discovering the gating inputs based on inverting and non-inverting methods. By including “clock gating” we still reduce the dynamic power and leakage power especially for sequential circuits and also used to some small combinational circuits.

DEMULTIPLEX THE SSB SIGNAL WITHOUT THE INTERFERENCES BETWEEN THE EVEN AND THE ODD SUBCHANNELS

This letter studies the interference between the even and the odd subchannels in the interleaved multiplexing optical fast orthogonal frequency-division multiplexing system, which is caused by the non-orthogonal demultiplexing transform at the receiver. To eliminate this interference, frequency and timing off-sets are introduced deliberately at the receiver to form orthogonal bases, which coincide with the discrete cosine and sine transforms of type- IV. Thus, the symbols can be demultiplexed at the receiver without any interference between subchannels, and the proposed receiver design can be implemented efficiently. Finally, analysis and simulation are provided to verify its feasibility and the ability to eliminate such interference.

DESIGN &ANALYSIS OF DUAL STACK METHOD FOR FUTURE TECHNOLOGIES

As low power circuits are most popular now a days as the scaling increase the leakage power in the circuit also increases rapidly so for removing these kind of leakages and to provide a better power efficiency we are using many types of power gating techniques. In this paper we are going to analyse the different types of flip-flops using different types of power gated circuits using low power VLSI design techniques and we are going to display the comparison results between different nanometer technologies. The NMOS1mulations were done using Microwind Layout Editor & DSCH software and the results were given below.

A DESIGN OF AREA AND POWER EFFICIENT HIGH SPEED DATA PATH LOGIC SYSTEM

Carry Select Adder (CSLA) is one of the fastest adders use in many data-processing processors to perform fast arithmetic functions. From the structure of the CSLA, it is clear that there is scope for reducing the area and power consumption in the CSLA. This work uses a simple and efficient gate-level modification to significantly reduce the area and power of the CSLA. Based on this modification 8-, 16-, 32-, and 64-b square-root CSLA (SQRT CSLA) architecture have been developed and compared with the regular SQRT CSLA architecture. The proposed design has reduced area and power as compared with the regular SQRT CSLA with only a slight increase in the delay. This work evaluates the performance of the proposed designs in terms of delay, area, power, and their products by hand with logical effort and through custom design and layout in 0.18- m CMOS process technology. The results analysis shows that the proposed CSLA structure is better than the regular SQRT CSLA.

ANALYSIS OF GRAPH CLUSTERING BASED NORMALIZED GRAPH CUT FOR IMAGE SEGMENTATION

The humans have sense organs to sense the outside world. In these organs eyes are vital. The human eyes capture the light from the outside world and save the information as images in the brain. The human brain analyses the image data and gets the required information from the surroundings. Images are most prominent and easy way of representing a data. The art of representing information through the images is as old as the civilized man. Moreover the images can convey a clear data representation than the words or some other representation. Image segmentation is an old research topic, which has gained its importance in the past four decades. There are several previous methods for the segmentation. But there is no optimal solution for the judgment. This is because there is no specific benchmark for the judgment. In our project we propose a new method for the segmentation of an image called “The Normalized Graph Cut Segmentation”. It is a global view concept which considers image as a graph model. The segmentation is done by using the similarity measurement technique. The problems of over segmentation and effect of noise can be overcome by this technique. The method is tested for various test cases like the landscape images, texture based images, high density feature based images and the performance of the algorithm has been tabulated.