scholarly journals Design and Implementation of FIR Filter using Efficient MAC

2020 ◽  
Vol 9 (3) ◽  
pp. 878-881
Keyword(s):  
Finite Impulse Response ◽  
Optimization Technique ◽  
Vlsi Architecture ◽  
Building Blocks ◽  
Fir Filter ◽  
Total Power ◽  
Area Efficiency ◽  
Logic Optimization ◽  
Gate Count ◽  
Impulse Response Filter

The Design And Realization Of Efficient Multiplication And Accumulation Unit (MAC) Of A Digital FIR Filter Has Substantial Influence In Designing A Well-Organized Finite Impulse Response Filter As It Is Used To Compute The Filter Response. Area Efficiency In An FIR Filter Can Be Achieved By Reducing The Gate Count Of Either Multiplier Unit Or An Adder Unit Or Both The Units Since They Are The Basic Building Blocks Of FIR Filter. This Paper Presents A VLSI Architecture For A 4-Tap FIR Filter Which Is Designed By Using Efficient Adder And A Multiplier Employing Logic Optimization Technique. Area For MAC Based FIR Filter Employing Vedic-CSLALOT Is Improved By 11.959% When Compared To Hierarchy-SQRT-CSLA. Total Power For MAC Based FIR Filter Employing Vedic-CSLALOT Is Improved By 13.15% As Against To Hierarchy-SQRT-CSLA.

scholarly journals Area and Power Potent VLSI Architecture for Modified CSLA with A Logic Optimization Technique

2019 ◽  
Vol 8 (12) ◽  
pp. 2873-2879 ◽  
Keyword(s):  
Optimization Technique ◽  
Vlsi Architecture ◽  
Performance Constraints ◽  
Area Efficiency ◽  
Logic Optimization ◽  
Ripple Carry Adder ◽  
Overall Performance ◽  
Carry Select Adder ◽  
The Cost ◽  
Area Efficient

Through generations, in an endeavor to pioneer innovative circuit designs, an adder is having the greatest importance as it is a basic building block to decide the system’s overall performance. Wide varieties of adders are used for a plethora of applications in the field of Signal Processing and VLSI systems. Most predominantly used Speed efficient architecture for performing n-bit addition in VLSI applications is Square Root Carry Select Adder (SQRT-CSLA) as it pre-computes the carry and sum by assuming input carry as ‘zero’ and ‘one’. But the overall area usage is high as it uses more number of full adders when compared to Ripple Carry Adder. Though, the existing adder designing techniques are area efficient, there is still scope to achieve area efficiency as area decides the cost of the VLSI Systems. Not only area-efficient but also power potent architectures are required to accelerate the overall performance of the VLSI systems. To meet these objectives, this paper proposes an efficient VLSI architecture for carry select adder by using logic optimization technique addressing performance constraints. The proposed architecture is designed and implemented using cadence encounter tool for different data widths ranging from 16 bits to 128 bits. The performance of the proposed 128-bit architecture achieves an area improvement of 63.43% and a power improvement of 71.00923% when compared to 128-bit SQRT-CSLA architecture

Optimized DA-reconfigurable FIR filters for software defined radio channelizer applications

Circuit World ◽  
2021 ◽  
Vol ahead-of-print (ahead-of-print) ◽  
Author(s):  
C. Srinivasa Murthy ◽  
K. Sridevi
Keyword(s):  
Energy Efficiency ◽  
Power Dissipation ◽  
Software Defined Radio ◽  
Filter Design ◽  
Finite Impulse Response ◽  
Software Tool ◽  
Building Blocks ◽  
Fir Filter ◽  
Content Type ◽  
Filter Length

Purpose In this paper, the authors present different methods for reconfigurable finite impulse response (RFIR) filter design. Distributed arithmetic (DA)-based reconfigurable FIR filter design is suitable for software-defined radio (SDR) applications. The main contribution of reconfiguration is reuse of registers, multipliers, adders and to optimize various parameters such as area, power dissipation, speed, throughput, latency and hardware utilizations of flip-flops and slices. Therefore, effective design of building blocks will be optimized for RFIR filter with all the above parameters. Design/methodology/approach The modified, direct form register structure of FIR filter contributes the reuse concept and allows utilization of less number of registers and parallel computation operations. The disadvantage of DA and other conventional methods is delay increases proportionally with filter length. This is due to different partial products generated by adders. The usage of adder and multipliers in DA-FIR filter restricts the area and power dissipation because of their complexity of generation of sum and carry bits. The hardware implementation time of an adder can be reduced by parallel prefix adder (PPA) usage based on Ling equation. PPA uses shift-add multiplication, which is a repetitive process of addition, and this process is known as Bypass Zero feed multiplicand in direct multiplication, and the proposed technique optimizes area-power product efficiently. The modified DA (MDA)-based RFIR filter is designed for 64 taps filter length (N). The design is developed by using Verilog hardware description language and implemented on field-programmable gate array. Also, this design validates SDR channel equalizer. Findings Both RFIR and SDR are integrated as single system and implemented on Artix-7 development board of XC7A100tCSG324 and exploited the advantages in area-delay, power-speed products and energy efficiency. The theoretical and practical comparisons have been carried out, and the results are compared with existing DA-RFIR designs in terms of throughput, latency, area-delay, power-speed products and energy efficiency, which are improved by 14.5%, 23%, 6.5%, 34.2% and 21%, respectively. Originality/value The DA-based RFIR filter is validated using Chipscope Pro software tool on Artix-7 FPGA in Xilinx ISE design suite and compared constraint parameters with existing state-of-art results. It is also tested the filtering operation by applying the RFIR filter on Audio signals for removal of noisy signals and it is found that 95% of noise signals are filtered effectively.

scholarly journals DESIGN AND IMPLEMENTATION OF ASYNCHRONOUS FIR FILTER

2013 ◽  
pp. 166-169
Author(s):  
N. HIMABINDU ◽  
ROHINI DESHPANDE
Keyword(s):  
Finite Impulse Response ◽  
Digital Signal ◽  
Fir Filter ◽  
Sampled Data ◽  
Analog To Digital ◽  
Asynchronous Logic ◽  
Uniform Sampling ◽  
Sampled Signal ◽  
Impulse Response Filter ◽  
Low Activity

This paper presents the architecture of a micropipeline asynchronous digital signal processing chain coupled to non-uniformly sampled data in time. Non-uniform sampling has been proven to be a better scheme than the uniform sampling to sample low activity signals. With such signals, it generates fewer samples, which means less data to process and lower power consumption. In addition, it is well-known that asynchronous logic is a low power technology. We focus on a Finite Impulse Response filter (FIR) applied to this non-uniform sampled signal obtained from an asynchronous analog to digital converter (A-ADC). The FIR filter blocks are implemented using verilog code.

scholarly journals Design and implementation of DA FIR filter for bio-inspired computing architecture

2021 ◽  
Vol 11 (2) ◽  
pp. 1709
Author(s):  
B. U. V. Prashanth ◽  
Mohammed Riyaz Ahmed ◽  
Manjunath R. Kounte
Keyword(s):  
Impulse Response ◽  
Integrated Circuit ◽  
High Speed ◽  
Finite Impulse Response ◽  
Fir Filter ◽  
Optimized Design ◽  
Tightly Coupled ◽  
Hardware Description ◽  
Impulse Response Filter ◽  
Performance Timing

This paper elucidates the system construct of DA-FIR filter optimized for design of distributed arithmetic (DA) finite impulse response (FIR) filter and is based on architecture with tightly coupled co-processor based data processing units. With a series of look-up-table (LUT) accesses in order to emulate multiply and accumulate operations the constructed DA based FIR filter is implemented on FPGA. The very high speed integrated circuit hardware description language (VHDL) is used implement the proposed filter and the design is verified using simulation. This paper discusses two optimization algorithms and resulting optimizations are incorporated into LUT layer and architecture extractions. The proposed method offers an optimized design in the form of offers average miminimizations of the number of LUT, reduction in populated slices and gate minimization for DA-finite impulse response filter. This research paves a direction towards development of bio inspired computing architectures developed without logically intensive operations, obtaining the desired specifications with respect to performance, timing, and reliability.

scholarly journals CSHM Multiplier and Radix-256 Algorithm using Fir Filter Design

2019 ◽  
Vol 8 (11S) ◽  
pp. 822-825
Keyword(s):  
Filter Design ◽  
Finite Impulse Response ◽  
Fir Filter ◽  
Partial Product ◽  
Unit Of Measurement ◽  
Element Addition ◽  
Fir Filter Design ◽  
Impulse Response Filter ◽  
Computation Sharing ◽  
Free Element

The Rredundant Binary (RB) systems are wellliked for the reason that of its distinctive carry broadcast free addition. Thus a specific filter called as Finite Impulse Response filter computes its yield exploitation multiply& accumulation process. At intervals the reward work, a FIR filter supported to new higher radix-256 and chemical element arithmetic is implemented. The employment of radix-256 booth secret writing cut down the amount of partial product rows in any multiplication by eight fold. Present work inputs and coefficients unit of measurement thought-about of 16-bit. Hence, entirely two partial product rows unit of quantity obtained in Redundant Binary (RB) kind for both input and constant multiplications. These two partial product rows unit of measurement added exploitation carry free element addition. The final output is converted back to Natural Binary (NB). The planned number technique for FIR filter is compared with Computation Sharing Multiplier (CSHM) implementation.

Implement Multichannel Fractional Sample Rate Convertor using Genetic Algorithm

2021 ◽  
pp. 482-494
Author(s):  
Vivek Jain ◽  
Navneet Agrawal
Keyword(s):  
Genetic Algorithm ◽  
Power Consumption ◽  
Hamming Distance ◽  
Finite Impulse Response ◽  
Total Power ◽  
Dynamic Power ◽  
Cmos Transistor ◽  
Sample Rate ◽  
Main Component ◽  
Impulse Response Filter

In this paper reduce power of multichannel fractional sample rate convertor by minimized hamming distance between consecutive coefficients of filter using Genetic algorithm. The main component of multichannel fractional sample rate convertor is Cascaded multiple architecture finite impulse response filter (CMFIR filter). CMFIR is implemented by cascading of cascaded integrator-comb (CIC) & multiply accumulate architecture (MAC) FIR filter. Genetic algorithm minimizes the hamming distance between consecutive coefficients of CMFIR filter. By Minimizing the hamming distance of consecutive filter coefficient reduces the transaction from 0 to 1 or 1 to 0. These techniques reduce the switching activity of CMOS transistor which is directly reduces Dynamic power consumption by multichannel sample rate convertor, it also minimizes the total power consumption of multichannel fractional sample rate convertor. later than use genetic algorithm on 1 to 128 channel Down sample rate convertor total power reduced by 3.44% to 61.56%, dynamic power reduced by 9.09% to 56.25% .1 to 128 channel Up sample rate convertor total power reduced by 2.81% to 45.42%, dynamic power reduced by 4.76% to 56%, 1 to 128 channel fractional sample rate convertor total power reduced by 1.44% to 17.17%, dynamic power reduced by 6.25% to 19.92%.

scholarly journals DESIGN OF FIR FILTER USING LOOK UP TABLE AND MEMORY BASED APPROACH

2015 ◽  
pp. 103-106
Author(s):  
A. SIRISHA ◽  
P. BALANAGU ◽  
N. SURESH BABU
Keyword(s):  
Digital Filters ◽  
Finite Impulse Response ◽  
Logic Gate ◽  
Fir Filter ◽  
Analog Filters ◽  
Finite Precision ◽  
Filter Performance ◽  
Look Up Table ◽  
Gate Count ◽  
Finite Precision Arithmetic

The main objective of this Paper is to develop Finite Impulse Response (FIR) Filter using look-up table (LUT) and memory based processor. The configuration is to reduce memory size, logic gate count and improve the speed of operation. Digital filters are becoming ubiquitous in audio applications. As a result, good digital filter performance is important to audio system design. Digital filters differ from conventional analog filters by their use of finite precision to represent signals and coefficients and finite precision arithmetic to compute the filter response. In this Paper, FIR filter is implemented in Xilinx ise using VHDL language. VHDL coding for the FIR filter is implemented in this Paper and waveforms are observed through simulation.

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