scholarly journals Enhanced Optimization of Edge Detection for High Resolution Images Using Verilog Hardware Description Language with Low Power Consumption and Less Hardware Technology

2016 ◽  
Vol 5 (4) ◽  
pp. 363-373
Author(s):  
Manikyala Rao T ◽  
Praveen Chakravarthy B. H ◽  
Sushma R ◽  
Parameswara Rao G
Keyword(s):  
High Resolution ◽  
Power Consumption ◽  
Edge Detection ◽  
Low Power ◽  
Hardware Description Language ◽  
Low Power Consumption ◽  
Description Language ◽  
High Resolution Images ◽  
Hardware Description ◽  
Verilog Hardware Description Language

scholarly journals Leakage Power Consumption of Address Register Interfacing with Different Families of FPGA

2019 ◽  
Vol 8 (9S2) ◽  
pp. 512-514
Keyword(s):  
Power Consumption ◽  
Leakage Power ◽  
The Other ◽  
Hardware Description Language ◽  
Description Language ◽  
Power Variation ◽  
Address Register ◽  
Hardware Description ◽  
Verilog Hardware Description Language

In this paper, we are designing an address register which is sensitive towards rising in voltage. We analysed the power variation of address register on Xilinx 14.1 ISE Design Suite and the code of address register is written in Verilog hardware description language. In this paper, we have used two FPGA of two different families, one is of Virtex family which is Virtex 6 and the other is of Spartan family which is Spartan 6, to study the power consumption of address register. We have observed the different on chips power which are consumed by address register by varying the voltage from 0.75V to 2V for Virtex 6 FPGA and 0.75V to 3V for Spartan 6 FPGA and we observed that when we lower the voltage, lower will be the power consumption. At 2V, Virtex 6 FPGA stops working and the interface of address register with FPGA burns out. For Spartan 6 FPGA, the same happens at 3V voltage.

Improved Redundant Binary Adder Realization in FPGA

2021 ◽  
pp. 2150287
Author(s):  
Satya Ranjan Sahu ◽  
Bandan Kumar Bhoi ◽  
Manoranjan Pradhan
Keyword(s):  
Propagation Delay ◽  
Hardware Description Language ◽  
Binary Number ◽  
Performance Parameters ◽  
Description Language ◽  
Hardware Description ◽  
Verilog Hardware Description Language

This paper presents the design of improved redundant binary adder (IRBA) by utilizing positive–negative encoding rules in FPGA platform. The proposed design deals with inverted encoding of negative binary (IEN) and positive binary number to get addition result using readily available standard hardware module. The Verilog hardware description language is used as design entry for synthesis of the proposed architecture in Xilinx ISE Desisn Suite 14.4 software. This structure is realized on Vertex-4 xc4vfx12-12sf363 FPGA device. The proposed IRBA is found to be time efficient in comparison with the performance parameters such as propagation delay and area over previous reported architecture.

A Portable and High-Resolution System for Sleep Apnea Monitoring

2013 ◽  
Vol 753-755 ◽  
pp. 2369-2373
Author(s):  
Yu Xuan Hu ◽  
Yi Hu ◽  
Shu Ming Ye ◽  
Xiao Xiang Zheng
Keyword(s):  
Sleep Apnea ◽  
High Resolution ◽  
Power Consumption ◽  
Low Power ◽  
Monitoring System ◽  
Sleep Apnea Syndrome ◽  
Low Power Consumption ◽  
Practical Applications ◽  
Obstructive Sleep ◽  
Apnea Monitoring

As a major indicator of Obstructive Sleep Apnea Syndrome (OSAS) in clinical diagnosis, the monitoring of sleep apnea plays an important role in medical treatments of modern society. This paper proposes a portable sleep apnea monitoring system, which is of high-precision and low-power consumption, and capable of performing the long-term monitoring of OSAS patients multiple physiological parameters in clinical treatments. In the system, the AC modulated detection is adopted, and low amplification ratios are utilized in forestage and a high-resolution AD converter is designed in post-stages. Thus, it is able to acquire, analyze, and process physiological signals in real-time. In addition, ultralow-power chips are used in control system to save the power consumption. The experimental results show that our monitoring system has the strengths of high stability, low-power consumption (peak current90mA), and strong anti-interference ability, which demonstrates the potential in practical applications.

Low Power Consumption Technology for Ultra-High Resolution Mobile Display by Using RGBW System

2013 ◽  
Vol E96.C (11) ◽  
pp. 1367-1372 ◽  
Author(s):  
Akira SAKAIGAWA ◽  
Masaaki KABE ◽  
Tsutomu HARADA ◽  
Fumitaka GOTO ◽  
Naoyuki TAKASAKI ◽  
...  
Keyword(s):  
High Resolution ◽  
Power Consumption ◽  
Low Power ◽  
Low Power Consumption
Sign in / Sign up

Export Citation Format

Share Document