A 80Ms/sec 10bit PIPELINED ADC Using 1.5Bit Stages And Built-in Digital Error Correction Logic
2011 ◽
Vol 2
(3)
◽
pp. 39-49
2020 ◽
Vol 981
◽
pp. 032046
2009 ◽
Vol 3
(2-3)
◽
pp. 185-198
◽
1981 ◽
Vol 128
(1)
◽
pp. 15
1990 ◽
Vol 137
(6)
◽
pp. 431
2012 ◽
Vol 2
(9)
◽
pp. 162-165