scholarly journals A 80Ms/sec 10bit PIPELINED ADC Using 1.5Bit Stages And Built-in Digital Error Correction Logic

2011 ◽  
Vol 2 (3) ◽  
pp. 39-49
Author(s):  
Prasad Rao ◽  
Lal Kishore
Author(s):  
Y. Srikanth ◽  
Ch. Rajendra Prasad ◽  
Koteshwar Rao Danthamala ◽  
P. Ramchandar Rao ◽  
A. Chakradhar

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