scholarly journals Gain error correction scheme for multiply-by-two gain amplifier in pipelined ADC

Author(s):  
Y.P. Lee ◽  
R.L. Geiger
Author(s):  
Y. Srikanth ◽  
Ch. Rajendra Prasad ◽  
Koteshwar Rao Danthamala ◽  
P. Ramchandar Rao ◽  
A. Chakradhar

Author(s):  
Hikmat N. Abdullah ◽  
Thamir R. Saeed ◽  
Asaad H. Sahar

An effective error-correction scheme based on normalized correlation for a non coherent chaos communication system with no redundancy bits is proposed in this paper. A modified logistic map is used in the proposed scheme for generating two sequences, one for every data bit value, in a manner that the initial value of the next chaotic sequence is set by the second value of the present chaotic sequence of the similar symbol. This arrangement, thus, has the creation of successive chaotic sequences with identical chaotic dynamics for error correction purpose. The detection symbol is performed prior to correction, on the basis of the suboptimal receiver which anchors on the computation of the shortest distance existing between the received sequence and the modified logistic map’s chaotic trajectory. The results of the simulation reveal noticeable Eb/No improvement by the proposed scheme over the prior to the error- correcting scheme with the improvement increasing whenever there is increase in the number of sequence N. Prior to the error-correcting scheme when N=8, a gain of 1.3 dB is accomplished in E<sub>b</sub>/N<sub>o</sub> at 10<sup>-3 </sup>bit error probability. On the basis of normalized correlation, the most efficient point in our proposed error correction scheme is the absence of any redundant bits needed with minimum delay procedure, in contrast to earlier method that was based on suboptimal method detection and correction. Such performance would render the scheme good candidate for applications requiring high rates of data transmission.


2019 ◽  
Vol 13 (2) ◽  
pp. 219-225
Author(s):  
Jupinder Kaur ◽  
Prince Prabhakar ◽  
Anil Singh ◽  
Alpana Agarwal

Electronics ◽  
2019 ◽  
Vol 8 (12) ◽  
pp. 1551 ◽  
Author(s):  
Jianwen Li ◽  
Xuan Guo ◽  
Jian Luan ◽  
Danyu Wu ◽  
Lei Zhou ◽  
...  

This paper presents a four-channel time-interleaved 3GSps 12-bit pipelined analog-to-digital converter (ADC). The combination of master clock sampling and delay-adjusting is adopted to remove the time skew due to channel mismatches. An early comparison scheme is used to minimize the non-overlapping time, where a custom-designed latch is developed to replace the typical non-overlapping clock generator. By using the dither capacitor to generate an equivalent direct current input, a zero-input-based calibration is developed to correct the capacitor mismatch and inter-stage gain error. Fabricated in a 40 nm CMOS process, the ADC achieves a signal-to-noise-and-distortion ratio (SNDR) of 57.8 dB and a spurious free dynamic range (SFDR) of 72 dB with a 23 MHz input tone. It can achieve an SNDR above 52.3 dB and an SFDR above 61.5 dB across the entire first Nyquist zone. The differential and integral nonlinearities are −0.93/+0.73 least significant bit (LSB) and −2.8/+4.3 LSB, respectively. The ADC consumes 450 mW powered at 1.8V, occupies an active area of 3 mm × 1.3 mm. The calculated Walden figure of merit reaches 0.44 pJ/step.


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