The Design and Implementation of Inverter Power Supply with FGS for Sulfur Lamp

2005 ◽  
Vol 19 (3) ◽  
pp. 10-16
Keyword(s):  
Power Supply ◽  
Design And Implementation ◽  
Inverter Power Supply

Study of Induction Heating Power Supply Based on 74HC4046

2014 ◽  
Vol 1008-1009 ◽  
pp. 663-667 ◽  
Author(s):  
Yan Cui ◽  
Xiao Jun He ◽  
Ze Ping Lin ◽  
Qing Bin Chen ◽  
Wei Hao Yang ◽  
...  
Keyword(s):  
Resonance Frequency ◽  
Induction Heating ◽  
Power Supply ◽  
Simulation Experiment ◽  
Tracking System ◽  
Output Frequency ◽  
Phase Compensation ◽  
Frequency Tracking ◽  
Iron Load ◽  
Inverter Power Supply

According to the change of resistivity and magnetic permeability of iron load which will influence the resonance frequency in the process of induction heating, this paper presents a frequency tracking system based on the 74HC4046. It can control the output frequency of the power supply in real time, and make the power output frequency to trace the resonance frequency of load. This paper also analyses the phase compensation of the control system, and proposes a new way of phase compensation. The corresponding simulation experiment is done finally. It provides the theory basis to analyze and design an inverter power supply.

Design and Implementation of a 12-Bit 100MS/s ADC

2012 ◽  
Vol 229-231 ◽  
pp. 1507-1510
Author(s):  
Xiang Ning Fan ◽  
Hao Zheng ◽  
Yu Tao Sun ◽  
Xiang Yan
Keyword(s):  
Power Consumption ◽  
Power Supply ◽  
Stage Structure ◽  
Digital Calibration ◽  
Cmos Process ◽  
Pipelined Adc ◽  
Dynamic Comparator ◽  
Flash Adc ◽  
Design And Implementation ◽  
Two Stages

In this paper, a 12-bit 100MS/s pipelined ADC is designed. Capacitance flip-around structure is used in sample and hold circuit, and bootstrap structure is adopted in sampling switch which has high linearity. Progressively decreasing technology is used to reduce power consumption and circuit area, where 2.5bit/stage structure is used in the first two stages, 1.5bit/stage structure is used for 3rd to 8th stages, and at the end of the circuit is a 2bit-flash ADC. Digital calibration is designed to eliminate the offset of comparators. Switched-capacitor dynamic comparator structure is used to further reduce the power consumption. The ADC is implemented by using TSMC 0.18m CMOS process with die area be 1.23mm×2.3mm. SNDR and SFDR are 65dB and 71.3dB, when sampling at 100MHz sampling clock. The current of the circuit is 96mA under 1.8V power supply.

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