scholarly journals Optimization Simulation programming for NoC

2019 ◽  
pp. 13-18
Author(s):  
Dhafer Sabah Yaseen
Keyword(s):  
Software Tool ◽  
Multiprocessor Systems ◽  
Performance Parameters ◽  
Promising Alternative ◽  
Networks On Chip ◽  
Communication Links ◽  
Optimization Simulation ◽  
On Chip ◽  
Ip Blocks ◽  
Bus Architecture

The article presents the concept of networks-on-chip (NoCs) as a promising alternative to communication subsystem for multiprocessor systems with bus architecture. The networks simulator developed as important software tool to estimate NoC performance parameters. The results of approbation of the developed simulator are reliance of the number of hops on the NoC dimension for mesh and torus topologies, as well as the dependences of communication links workload on the frequency, with which IP blocks generate messages. Its possibilities are considered and the accepted results are given.

scholarly journals Development of a software simulator of networks on a chip

2011 ◽  
Vol 16 (4) ◽  
pp. 48-52
Author(s):  
D.A. Fes'kov ◽  
A.YU. Romanov
Keyword(s):  
Software Tool ◽  
Multiprocessor Systems ◽  
Performance Parameters ◽  
Promising Alternative ◽  
Networks On Chip ◽  
On Chip ◽  
Bus Architecture

The article presents the concept of networks-on-chip (NoC) as a promising alternative to communication subsystem for multiprocessor systems with bus architecture. The networks simulator developed as a necessary software tool to evaluate NoC performance parameters. Its possibilities are considered and the results of its approbation are given

scholarly journals Diseño e Implementación de un Multiprocessor Systems-on-Chip (MPSoC) Interconectado por una Networks-on-Chip (NoC)

MASKAY ◽  
2013 ◽  
Vol 3 (1) ◽  
pp. 40
Author(s):  
Wilson Mauricio Chicaiza ◽  
Daniel Gonzalo Verdesoto
Keyword(s):  
Multiprocessor Systems ◽  
Networks On Chip ◽  
Systems On Chip ◽  
On Chip ◽  
Medios De Comunicacion

En el presente documento se presenta una breve caracterización de los medios de comunicación empleados en arquitecturas multiprocesadas. Esta caracterización tiene como objetivo principal el mostrar un nuevo modelo de comunicación basado en conmutación de paquetes a los cuales se les denomina como Networks-On-Chip (NoC). Esta publicación muestra una arquitectura de red llamada NoC Hermes, la cual fue interconectada a un Multiprocessor-Systems-on-Chip (MPSoC) compuesto de cuatro procesadores MicroBlaze. Está conexión se la realizó gracias al diseño y desarrollo de una Interfaz de Red generada en código VHDL. Por medio de la Interfaz de Red se consiguió que los procesadores MicroBlaze interactúen con los Switches de Hermes a fin de crear una arquitectura multiprocesada interconectada por una NoC. Con el motivo de realizar comparaciones también se creó otra arquitectura de multiprocesadores interconectados por buses. Para ambas arquitecturas se desarrolló una aplicación de Esteganografía enla que existe multiprocesamiento de dos procesadores trabajando simultáneamente. Lamentablemente sobre dicha aplicación no fue posible medir directamente la latencia y el consumo de energía, razón por la cual se utilizó simuladores que permitieron estimar dichas mediciones.

scholarly journals Design of AMBA AXI4 protocol for System-on-Chip communication

2012 ◽  
pp. 38-42
Author(s):  
Shaila S Math ◽  
Manjula R B
Keyword(s):  
System On Chip ◽  
Hardware Description Language ◽  
Test Cases ◽  
Description Language ◽  
Write Response ◽  
Hardware Description ◽  
Simulation Results ◽  
On Chip ◽  
Ip Blocks ◽  
Bus Architecture

Advanced microcontroller bus architecture (AMBA) protocol family provides metric-driven verification of protocol compliance, enabling comprehensive testing of interface intellectual property (IP) blocks and system-on-chip (SoC) designs. The AMBA advanced extensible interface 4 (AXI4) update to AMBA AXI3 includes the following: support for burst lengths up to 256 beats, updated write response requirements, removal of locked transactions and AXI4 also includes information on the interoperability of components. AMBA AXI4 protocol system supports 16 masters and 16 slaves interfacing. This paper presents a work aimed to design the AMBA AXI4 protocol modeled in Verilog hardware description language (HDL) and simulation results for read and write operation of data and address are shown in Verilog compiler simulator (VCS) tool. The operating frequency is set to 100MHz. Two test cases are run to perform multiple read and multiple write operations. To perform single read operation module takes 160ns and for single write operation it takes 565ns.

scholarly journals Cluster-based topologies for 3D Networks-on-Chip using advanced inter-layer bus architecture

2013 ◽  
Vol 79 (4) ◽  
pp. 475-491 ◽  
Author(s):  
Masoumeh Ebrahimi ◽  
Masoud Daneshtalab ◽  
Pasi Liljeberg ◽  
Juha Plosila ◽  
Hannu Tenhunen
Keyword(s):  
Networks On Chip ◽  
On Chip ◽  
Bus Architecture ◽  
3D Networks

Energy-Performance Analysis and Optimization for Networks-on-Chip

2014 ◽  
Vol 36 (5) ◽  
pp. 988-1003 ◽  
Author(s):  
Shuai ZHANG ◽  
Feng-Long SONG ◽  
Dong WANG ◽  
Zhi-Yong LIU ◽  
Dong-Rui FAN
Keyword(s):  
Performance Analysis ◽  
Energy Performance ◽  
Networks On Chip ◽  
On Chip
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