High-speed Clock and Data Recovery System with Segmented Slew-rate Control Circuit for High-linearity in 65 nm CMOS Process

2021 ◽  
Vol 21 (3) ◽  
pp. 199-205
Author(s):  
Kyunghwan Min ◽  
Sanggeun Lee ◽  
Taehyoun Oh
Keyword(s):  
Rate Control ◽  
High Speed ◽  
Clock And Data Recovery ◽  
Control Circuit ◽  
Data Recovery ◽  
Cmos Process ◽  
Slew Rate ◽  
High Linearity ◽  
Recovery System

Design of the Circuits for a CMOS CAN Transceiver Chip with Slew Rate Control

2012 ◽  
Vol 433-440 ◽  
pp. 1895-1902
Author(s):  
Hui Hui Zhan ◽  
Shao Xin Zong ◽  
Xiu Gang Han ◽  
Chuan Nan Li
Keyword(s):  
Rate Control ◽  
High Speed ◽  
Short Circuit ◽  
Current Source ◽  
Control Circuit ◽  
Cmos Process ◽  
Slew Rate ◽  
Output Stage ◽  
Middle Stage ◽  
Small Delay

In this paper, the design of a CMOS transceiver circuits for CAN bus based on 0.5μm n-well CMOS process is presented. It has the advantages of high speed, high driving capability and strong anti-interference capability. It is mainly made up of a receiver and a transmitter which includes the input stage circuit, the middle stage circuit, the slew rate control circuit and the output stage circuit. With five cascaded inverters, the middle stage circuit can provide a high driving current and a small delay. In the slew rate control circuit, due to a variable charge or discharge current source, the slew rate of output signal could be adjusted continuously by an external resistance Rs. So it is very convenient for the chip to be applied in different modes and at different rates. The output stage circuit has the function of short-circuit protection, overvoltage and undervoltage protection. The receiver circuit is a hysteresis comparator introduced by a positive feedback to reduce the differential noise effectively, and it has a small temperature coefficient too. Hspice simulation results show that the transceiver meets the ISO-11898 standards and could operate at the rate of 1Mbit/s.

scholarly journals Design of clock and data recovery system’s behavioral model for high speed transceivers of serial interfaces

2019 ◽  
Vol 30 ◽  
pp. 03013
Author(s):  
Alexey V. Dubinskiy ◽  
Denis A. Domozhakov ◽  
Nikolay Yu. Rannev
Keyword(s):  
Data Transmission ◽  
High Speed ◽  
Estimation Error ◽  
Behavioral Model ◽  
Clock And Data Recovery ◽  
Data Recovery ◽  
Calculation Error ◽  
Model Structure ◽  
Receiver Block ◽  
Recovery System

This paper provides a parameterizable behavioral model of a clock and data recovery system (CDR) based on phase-locked loop (PLL) for the receiver part of a high-speed serial interfaces. The model was used to calculate parameters and characteristics of the system as well as estimate their calculation error depending on the sub-circuit characteristics taken into account. A model structure was selected based on the obtained jitter estimation error. The model complies with all the accuracy and speed requirements to calculations of the characteristics of a PLL-CDR system for a receiver block with data transmission bit rates above 3.125 Gbit/s.

An all-digital semi-blind clock and data recovery system

2015 ◽  
Vol 46 (4) ◽  
pp. 273-284
Author(s):  
Mina Abdallah ◽  
Ahmed Eladawy ◽  
Ahmed Mohieldin
Keyword(s):  
Clock And Data Recovery ◽  
Data Recovery ◽  
Recovery System

scholarly journals A Robust High Speed Serial PHY Architecture With Feed-Forward Correction Clock and Data Recovery

2009 ◽  
Vol 44 (7) ◽  
pp. 1914-1926 ◽  
Author(s):  
William Redman-White ◽  
Martin Bugbee ◽  
Steve Dobbs ◽  
Xinyan Wu ◽  
Richard Balmford ◽  
...  
Keyword(s):  
High Speed ◽  
Clock And Data Recovery ◽  
Data Recovery ◽  
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