scholarly journals Approximate Reciprocal Square Root with Single - and Half-Precision Floats

2018 ◽  
Author(s):  
Matheus M. Susin ◽  
Lucas Wanner

In this work, we compared the precision, speed, and power consumption of the reciprocal square root of a single-precision floating point number, using different approximation techniques. We also devised an equivalent approximation for half-precision floating point numbers, and evaluated its performance across the whole range of positive non-zero 16-bit floating point values.

Author(s):  
Yuxuan Wang ◽  
Yuanyong Luo ◽  
Zhongfeng Wang ◽  
Qinghong Shen ◽  
Hongbing Pan

2005 ◽  
Vol 16 (11) ◽  
pp. 1811-1816 ◽  
Author(s):  
YORICK HARDY ◽  
WILLI-HANS STEEB ◽  
RUEDI STOOP

The core in most genetic algorithms is the bitwise manipulations of bit strings. We show that one can directly manipulate the bits in floating point numbers. This means the main bitwise operations in genetic algorithm mutations and crossings are directly done inside the floating point number. Thus the interval under consideration does not need to be known in advance. For applications, we consider the roots of polynomials and finding solutions of linear equations.


Author(s):  
Cezary J. Walczyk ◽  
Leonid V. Moroz ◽  
Jan L. Cieśliński

We present an improved algorithm for fast calculation of the inverse square root for single-precision floating-point numbers. The algorithm is much more accurate than the famous fast inverse square root algorithm and has a similar computational cost. The presented modification concern Newton-Raphson corrections and can be applied when the distribution of these corrections is not symmetric (for instance, in our case they are always negative).


Electronics ◽  
2021 ◽  
Vol 10 (16) ◽  
pp. 1988
Author(s):  
Yuheng Yang ◽  
Qing Yuan ◽  
Jian Liu

In this paper, we propose an efficient architecture of floating-point square-root circuit with low area cost, which is in accordance with the IEEE-754 standard. We extend the principle of the standard SRT algorithm so that the latency and area cost of the proposed circuit are linear with the radix. In addition, no extra computation cycles are required. With 65 nm technology, the area cost of the single-precision floating-point square-root circuit based on proposed architecture is only 6450.84 μm2, and the dynamic power consumption is only 0.764 mW at 300 MHz. The implementation results show that the proposed square-root circuit can reduce the area cost by 60%~90% compared with other designs in the literature.


2001 ◽  
Vol 01 (02) ◽  
pp. 217-230 ◽  
Author(s):  
M. GAVRILOVA ◽  
J. ROKNE

The main result of the paper is a new and efficient algorithm to compute the closest possible representable intersection point between two lines in the plane. The coordinates of the points that define the lines are given as single precision floating-point numbers. The novelty of the algorithm is the method for deriving the best possible representable floating point numbers: instead of solving the equations to compute the line intersection coordinates exactly, which is a computationally expensive procedure, an iterative binary search procedure is applied. When the required precision is achieved, the algorithm stops. Only exact comparison tests are needed. Interval arithmetic is applied to further speed up the process. Experimental results demonstrate that the proposed algorithm is on the average ten times faster than an implementation of the line intersection computation subroutine using the CORE library exact arithmetic.


Sign in / Sign up

Export Citation Format

Share Document