scholarly journals A Low-Cost High Radix Floating-Point Square-Root Circuit

Electronics ◽  
2021 ◽  
Vol 10 (16) ◽  
pp. 1988
Author(s):  
Yuheng Yang ◽  
Qing Yuan ◽  
Jian Liu
Keyword(s):  
Power Consumption ◽  
Low Cost ◽  
Floating Point ◽  
Square Root ◽  
Single Precision ◽  
Dynamic Power ◽  
Low Area ◽  
High Radix

In this paper, we propose an efficient architecture of floating-point square-root circuit with low area cost, which is in accordance with the IEEE-754 standard. We extend the principle of the standard SRT algorithm so that the latency and area cost of the proposed circuit are linear with the radix. In addition, no extra computation cycles are required. With 65 nm technology, the area cost of the single-precision floating-point square-root circuit based on proposed architecture is only 6450.84 μm2, and the dynamic power consumption is only 0.764 mW at 300 MHz. The implementation results show that the proposed square-root circuit can reduce the area cost by 60%~90% compared with other designs in the literature.

scholarly journals Approximate Reciprocal Square Root with Single - and Half-Precision Floats

2018 ◽  
Author(s):  
Matheus M. Susin ◽  
Lucas Wanner
Keyword(s):  
Power Consumption ◽  
Floating Point ◽  
Square Root ◽  
Single Precision ◽  
Approximation Techniques ◽  
Point Number ◽  
Floating Point Number ◽  
Floating Point Numbers

In this work, we compared the precision, speed, and power consumption of the reciprocal square root of a single-precision floating point number, using different approximation techniques. We also devised an equivalent approximation for half-precision floating point numbers, and evaluated its performance across the whole range of positive non-zero 16-bit floating point values.

scholarly journals Idleness-Aware Dynamic Power Mode Selection on the i.MX 7ULP IoT Edge Processor

2020 ◽  
Vol 10 (2) ◽  
pp. 19
Author(s):  
Alfio Di Mauro ◽  
Hamed Fatemi ◽  
Jose Pineda de Gyvez ◽  
Luca Benini
Keyword(s):  
Power Consumption ◽  
Power Management ◽  
Management Strategy ◽  
Low Cost ◽  
Mode Selection ◽  
Worst Case ◽  
Dynamic Power ◽  
Dynamic Tuning ◽  
Power Management Strategy ◽  
Power Mode

Power management is a crucial concern in micro-controller platforms for the Internet of Things (IoT) edge. Many applications present a variable and difficult to predict workload profile, usually driven by external inputs. The dynamic tuning of power consumption to the application requirements is indeed a viable approach to save energy. In this paper, we propose the implementation of a power management strategy for a novel low-cost low-power heterogeneous dual-core SoC for IoT edge fabricated in 28 nm FD-SOI technology. Ss with more complex power management policies implemented on high-end application processors, we propose a power management strategy where the power mode is dynamically selected to ensure user-specified target idleness. We demonstrate that the dynamic power mode selection introduced by our power manager allows achieving more than 43% power consumption reduction with respect to static worst-case power mode selection, without any significant penalty in the performance of a running application.

scholarly journals A Modification of the Fast Inverse Square Root Algorithm

Computation ◽  
2019 ◽  
Vol 7 (3) ◽  
pp. 41 ◽  
Author(s):  
Cezary J. Walczyk ◽  
Leonid V. Moroz ◽  
Jan L. Cieśliński
Keyword(s):  
Analytical Approach ◽  
Floating Point ◽  
Square Root ◽  
Approximate Evaluation ◽  
Single Precision ◽  
Seed Solution ◽  
Numerical Tests ◽  
Newton Raphson ◽  
Relative Errors ◽  
Magic Constant

We present a new algorithm for the approximate evaluation of the inverse square root for single-precision floating-point numbers. This is a modification of the famous fast inverse square root code. We use the same “magic constant” to compute the seed solution, but then, we apply Newton–Raphson corrections with modified coefficients. As compared to the original fast inverse square root code, the new algorithm is two-times more accurate in the case of one Newton–Raphson correction and almost seven-times more accurate in the case of two corrections. We discuss relative errors within our analytical approach and perform numerical tests of our algorithm for all numbers of the type float.

scholarly journals Modified Fast Inverse Square Root and Square Root Approximation Algorithms: The Method of Switching Magic Constants

Computation ◽  
2021 ◽  
Vol 9 (2) ◽  
pp. 21 ◽  
Author(s):  
Leonid V. Moroz ◽  
Volodymyr V. Samotyy ◽  
Oleh Y. Horyachyy
Keyword(s):  
Low Cost ◽  
Initial Approximation ◽  
Floating Point ◽  
Maximum Relative Error ◽  
Double Precision ◽  
Square Root ◽  
Simple Modification ◽  
Field Programmable ◽  
Complex Solutions ◽  
Good Trade

Many low-cost platforms that support floating-point arithmetic, such as microcontrollers and field-programmable gate arrays, do not include fast hardware or software methods for calculating the square root and/or reciprocal square root. Typically, such functions are implemented using direct lookup tables or polynomial approximations, with a subsequent application of the Newton–Raphson method. Other, more complex solutions include high-radix digit-recurrence and bipartite or multipartite table-based methods. In contrast, this article proposes a simple modification of the fast inverse square root method that has high accuracy and relatively low latency. Algorithms are given in C/C++ for single- and double-precision numbers in the IEEE 754 format for both square root and reciprocal square root functions. These are based on the switching of magic constants in the initial approximation, depending on the input interval of the normalized floating-point numbers, in order to minimize the maximum relative error on each subinterval after the first iteration—giving 13 correct bits of the result. Our experimental results show that the proposed algorithms provide a fairly good trade-off between accuracy and latency after two iterations for numbers of type float, and after three iterations for numbers of type double when using fused multiply–add instructions—giving almost complete accuracy.

scholarly journals Logic Design and Power Optimization of Floating-Point Multipliers

2022 ◽  
Vol 2022 ◽  
pp. 1-10
Author(s):  
Na Bai ◽  
Hang Li ◽  
Jiming Lv ◽  
Shuai Yang ◽  
Yaohua Xu
Keyword(s):  
Power Consumption ◽  
Power Optimization ◽  
Current Situation ◽  
Floating Point ◽  
Cell Process ◽  
Logic Design ◽  
Flowing Water ◽  
Partial Product ◽  
Standard Cell ◽  
Single Precision

Under IEEE-754 standard, for the current situation of excessive time and power consumption of multiplication operations in single-precision floating-point operations, the expanded boothwallace algorithm is used, and the partial product caused by booth coding is rounded and predicted with the symbolic expansion idea, and the partial product caused by single-precision floating-point multiplication and the accumulation of partial products are optimized, and the flowing water is used to improve the throughput. Based on this, a series of verification and synthesis simulations are performed using the SMIC-7 nm standard cell process. It is verified that the new single-precision floating-point multiplier can achieve a smaller power share compared to the conventional single-precision floating-point multiplier.

scholarly journals A Modification of the Fast Inverse Square Root Algorithm

2019 ◽  
Author(s):  
Cezary J. Walczyk ◽  
Leonid V. Moroz ◽  
Jan L. Cieśliński
Keyword(s):  
Computational Cost ◽  
Floating Point ◽  
Square Root ◽  
Single Precision ◽  
Fast Calculation ◽  
Newton Raphson ◽  
Floating Point Numbers ◽  
Improved Algorithm

We present an improved algorithm for fast calculation of the inverse square root for single-precision floating-point numbers. The algorithm is much more accurate than the famous fast inverse square root algorithm and has a similar computational cost. The presented modification concern Newton-Raphson corrections and can be applied when the distribution of these corrections is not symmetric (for instance, in our case they are always negative).

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