Design of an energy-efficient XNOR gate based on MTJ-based nonvolatile logic-in-memory architecture for binary neural network hardware

Binarized neural networks (BNNs), which have 1-bit weights and activations, are well suited for FPGA accelerators as their dominant computations are bitwise arithmetic, and the reduction in memory requirements means that all the network parameters can be stored in internal memory. However, the energy efficiency of these accelerators is still restricted by the abundant redundancies in BNNs. This hinders their deployment for applications in smart sensors and tiny devices because these scenarios have tight constraints with respect to energy consumption. To overcome this problem, we propose an approach to implement BNN inference while offering excellent energy efficiency for the accelerators by means of pruning the massive redundant operations while maintaining the original accuracy of the networks. Firstly, inspired by the observation that the convolution processes of two related kernels contain many repeated computations, we first build one formula to clarify the reusing relationships between their convolutional outputs and remove the unnecessary operations. Furthermore, by generalizing this reusing relationship to one tile of kernels in one neuron, we adopt an inclusion pruning strategy to further skip the superfluous evaluations of the neurons whose real output values can be determined early. Finally, we evaluate our system on the Zynq 7000 XC7Z100 FPGA platform. Our design can prune 51 percent of the operations without any accuracy loss. Meanwhile, the energy efficiency of our system is as high as 6.55 × 105 Img/kJ, which is 118× better than the best accelerator based on an NVDIA Tesla-V100 GPU and 3.6× higher than the state-of-the-art FPGA implementations for BNNs.

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An Energy-Efficient Time-Domain Binary Neural Network Accelerator with Error-Detection in 28nm CMOS

2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) ◽

10.1109/apccas50809.2020.9301692 ◽

2020 ◽

Author(s):

Yuxuan Du ◽

Xinchao Shang ◽

Weiwei Shan

Keyword(s):

Neural Network ◽

Time Domain ◽

Error Detection ◽

Energy Efficient ◽

Binary Neural Network

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DNN-Life: An Energy-Efficient Aging Mitigation Framework for Improving the Lifetime of On-Chip Weight Memories in Deep Neural Network Hardware Architectures

10.23919/date51398.2021.9473943 ◽

2021 ◽

Author(s):

Muhammad Abdullah Hanif ◽

Muhammad Shafique

Keyword(s):

Neural Network ◽

Energy Efficient ◽

Deep Neural Network ◽

Hardware Architectures ◽

Neural Network Hardware ◽

On Chip

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A 5.28-mm² 4.5-pJ/SOP Energy-Efficient Spiking Neural Network Hardware With Reconfigurable High Processing Speed Neuron Core and Congestion-Aware Router

IEEE Transactions on Circuits and Systems I Regular Papers ◽

10.1109/tcsi.2021.3112979 ◽

2021 ◽

pp. 1-14

Author(s):

Junran Pu ◽

Wang Ling Goh ◽

Vishnu P. Nambiar ◽

Ming Ming Wong ◽

Anh Tuan Do

Keyword(s):

Neural Network ◽

Processing Speed ◽

Energy Efficient ◽

Spiking Neural Network ◽

High Processing Speed ◽

Neural Network Hardware ◽

High Processing ◽

Congestion Aware

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ROBIN: A Robust Optical Binary Neural Network Accelerator

ACM Transactions on Embedded Computing Systems ◽

10.1145/3476988 ◽

2021 ◽

Vol 20 (5s) ◽

pp. 1-24

Author(s):

Febin P. Sunny ◽

Asif Mirza ◽

Mahdi Nikdast ◽

Sudeep Pasricha

Keyword(s):

Neural Network ◽

Energy Efficient ◽

Network Models ◽

Microring Resonator ◽

Memory Consumption ◽

Neural Network Models ◽

Domain Specific ◽

Binary Neural Network ◽

Optical Domain ◽

Time Overhead

Domain specific neural network accelerators have garnered attention because of their improved energy efficiency and inference performance compared to CPUs and GPUs. Such accelerators are thus well suited for resource-constrained embedded systems. However, mapping sophisticated neural network models on these accelerators still entails significant energy and memory consumption, along with high inference time overhead. Binarized neural networks (BNNs), which utilize single-bit weights, represent an efficient way to implement and deploy neural network models on accelerators. In this paper, we present a novel optical-domain BNN accelerator, named ROBIN , which intelligently integrates heterogeneous microring resonator optical devices with complementary capabilities to efficiently implement the key functionalities in BNNs. We perform detailed fabrication-process variation analyses at the optical device level, explore efficient corrective tuning for these devices, and integrate circuit-level optimization to counter thermal variations. As a result, our proposed ROBIN architecture possesses the desirable traits of being robust, energy-efficient, low latency, and high throughput, when executing BNN models. Our analysis shows that ROBIN can outperform the best-known optical BNN accelerators and many electronic accelerators. Specifically, our energy-efficient ROBIN design exhibits energy-per-bit values that are ∼4 × lower than electronic BNN accelerators and ∼933 × lower than a recently proposed photonic BNN accelerator, while a performance-efficient ROBIN design shows ∼3 × and ∼25 × better performance than electronic and photonic BNN accelerators, respectively.

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