scholarly journals Development of X-Band Transceiver MMIC’s Using GaN Technology

2019 ◽  
Vol 8 (2) ◽  
pp. 1-9
Author(s):  
O. Memioglu ◽  
O. Kazan ◽  
A. Karakuzulu ◽  
I. Turan ◽  
A. Gundel ◽  
...  
Keyword(s):  
Power Amplifiers ◽  
Noise Figure ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Rf Power ◽  
Rf Switch ◽  
X Band ◽  
Measurement Results ◽  
Noise Amplifier ◽  
Selection Of

This paper describes X-Band power amplifier (PA), low noise amplifier (LNA) and switches that can be used in transmit/receive modules which are developed with GaN technology. For Transmit chain two 25 W high power amplifiers that are tuned between 8-10 GHz and 10-12 GHz bands are designed. A low noise amplifier with 2 W survivability and less than 2dB noise figure is designed for receive chain Furthermore, an RF switch that is capable of withstanding 25 W RF power is developed for the selection of transmit or receive chains. Measurement results show that both power amplifiers produce 25 W of power. Low noise amplifier has more than 20 dB small signal gain with less than 2 dB noise figure. RF switch has 50 dB of isolation with less than 1 dB insertion loss.

scholarly journals Miniature Switchable Millimeter-Wave BiCMOS Low-Noise Amplifier at 120/140 GHz Using an HBT Switch

Micromachines ◽  
2019 ◽  
Vol 10 (10) ◽  
pp. 632 ◽  
Author(s):  
Julio Heredia ◽  
Miquel Ribó ◽  
Lluís Pradell ◽  
Selin Tolunay Wipf ◽  
Alexander Göritz ◽  
...  
Keyword(s):  
Noise Figure ◽  
Design Procedure ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Rf Switch ◽  
Area Reduction ◽  
Input Matching ◽  
Bicmos Technology ◽  
Noise Amplifier ◽  
Single Radio

A 120–140 GHz frequency-switchable, very compact low-noise amplifier (LNA) fabricated in a 0.13 µm SiGe:C BiCMOS technology is proposed. A single radio-frequency (RF) switch composed of three parallel hetero junction bipolar transistors (HBTs) in a common-collector configuration and a multimodal three-line microstrip structure in the input matching network are used to obtain a LNA chip of miniaturized size. A systematic design procedure is applied to obtain a perfectly balanced gain and noise figure in both frequency states (120 GHz and 140 GHz). The measured gain and noise figure are 14.2/14.2 dB and 8.2/8.2 dB at 120/140 GHz respectively, in very good agreement with circuit/electromagnetic co-simulations. The LNA chip and core areas are 0.197 mm2 and 0.091 mm2, respectively, which supposes an area reduction of 23.4% and 15.2% compared to other LNAs reported in this frequency band. The experimental results validate the design procedure and its analysis.

Measurement of a 270 GHz Low Noise Amplifier With 7.5 dB Noise Figure

2007 ◽  
Vol 17 (7) ◽  
pp. 546-548 ◽  
Author(s):  
T. Gaier ◽  
L. Samoska ◽  
A. Fung ◽  
W. R. Deal ◽  
V. Radisic ◽  
...  
Keyword(s):  
Noise Figure ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Noise Amplifier

scholarly journals A 0.18um CMOS Low Noise Amplifier for 3-5ghz UWB Receivers

2018 ◽  
Vol 7 (3.6) ◽  
pp. 84
Author(s):  
N Malika Begum ◽  
W Yasmeen
Keyword(s):  
Power Supply ◽  
Noise Figure ◽  
Cmos Technology ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Ultra Wideband ◽  
Noise Amplifier ◽  
5 Ghz ◽  
Chebyshev Filter ◽  
Minimum Noise

This paper presents an Ultra-Wideband (UWB) 3-5 GHz Low Noise Amplifier (LNA) employing Chebyshev filter. The LNA has been designed using Cadence 0.18um CMOS technology. Proposed LNA achieves a minimum noise figure of 2.2dB, power gain of 9dB.The power consumption is 6.3mW from 1.8V power supply.  

scholarly journals A 2.4 GHz low noise amplifier design at 130nm CMOS technology using common gate topology for WiFi / WiMAX application

2017 ◽  
Vol 7 (1.3) ◽  
pp. 69
Author(s):  
M. Ramana Reddy ◽  
N.S Murthy Sharma ◽  
P. Chandra Sekhar
Keyword(s):  
Noise Figure ◽  
Cmos Technology ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Low Power Consumption ◽  
Common Gate ◽  
Chip Size ◽  
Overall Performance ◽  
Amplifier Design ◽  
Noise Amplifier

The proposed work shows an innovative designing in TSMC 130nm CMOS technology. A 2.4 GHz common gate topology low noise amplifier (LNA) using an active inductor to attain the low power consumption and to get the small chip size in layout design. By using this Common gate topology achieves the noise figure of 4dB, Forward gain (S21) parameter of 14.7dB, and the small chip size of 0.26 mm, while 0.8mW power consuming from a 1.1V in 130nm CMOS gives the better noise figure and improved the overall performance.

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