scholarly journals A 2.4 GHz low noise amplifier design at 130nm CMOS technology using common gate topology for WiFi / WiMAX application

2017 ◽  
Vol 7 (1.3) ◽  
pp. 69
Author(s):  
M. Ramana Reddy ◽  
N.S Murthy Sharma ◽  
P. Chandra Sekhar
Keyword(s):  
Noise Figure ◽  
Cmos Technology ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Low Power Consumption ◽  
Common Gate ◽  
Chip Size ◽  
Overall Performance ◽  
Amplifier Design ◽  
Noise Amplifier

The proposed work shows an innovative designing in TSMC 130nm CMOS technology. A 2.4 GHz common gate topology low noise amplifier (LNA) using an active inductor to attain the low power consumption and to get the small chip size in layout design. By using this Common gate topology achieves the noise figure of 4dB, Forward gain (S21) parameter of 14.7dB, and the small chip size of 0.26 mm, while 0.8mW power consuming from a 1.1V in 130nm CMOS gives the better noise figure and improved the overall performance.

A wideband CMOS single-ended low noise amplifier employing negative resistance technique

2018 ◽  
Vol 32 (06) ◽  
pp. 1850068 ◽  
Author(s):  
Benqing Guo ◽  
Hongpeng Chen ◽  
Xuebing Wang ◽  
Jun Chen ◽  
Yueyue Li ◽  
...  
Keyword(s):  
Power Dissipation ◽  
Noise Figure ◽  
Cmos Technology ◽  
Negative Resistance ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Common Gate ◽  
Noise Amplifier ◽  
Maximal Gain ◽  
Resistance Structure

A wideband common-gate CMOS low noise amplifier with negative resistance technique is proposed. A novel single-ended negative resistance structure is employed to improve gain and noise of the LNA. The inductor resonating is adopted at the input stage and load stage to meet wideband matching and compensate gain roll-off at higher frequencies. Implemented in a 0.18 [Formula: see text]m CMOS technology, the proposed LNA demonstrates in simulations a maximal gain of 16.4 dB across the 3 dB bandwidth of 0.2–3 GHz. The in-band noise figure of 3.4–4.7 dB is obtained while the IIP3 of 5.3–6.8 dBm and IIP2 of 12.5–17.2 dBm are post-simulated in the designed frequency band. The LNA core consumes a power dissipation of 3.8 mW under a 1.5 V power supply.

scholarly journals Low Noise Amplifier with Improved Gain and Reduced Noise-Figure in 90nm CMOS Technology

2021 ◽  
pp. 85-94
Author(s):  
Dr. Rashmi S B ◽  
Mr. Raghavendra B ◽  
Mr. Sanketh V
Keyword(s):  
Reflection Coefficient ◽  
Noise Figure ◽  
Cmos Technology ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Ultra Wideband ◽  
Common Source ◽  
Frequency Range ◽  
Common Gate ◽  
Noise Amplifier

A CMOS low noise amplifier (LNA) for ultra-wideband (UWB) wireless applications is presented in this paper. The proposed CMOS low noise amplifier (LNA) is designed using common-gate (CG) topology as the first stage to achieve ultra-wideband input matching. The common-gate (CG) is cascaded with common- source (CS) topology with current-reused configuration to enhance the gain and noise figure (NF) performance of the LNA with low power. The Buffer stage is used as output matching network to improve the reflection coefficient. The proposed low noise amplifier (LNA) is implemented using CADENCE Virtuoso Analog and Digital Design Environment tool in 90nm CMOS technology. The LNA provides a forward voltage gain or power gain (S21) of 32.34dB , a minimum noise figure of 2dB, a reverse-isolation (S12) of less than - 38.74dB and an output reflection coefficient (S22) of less than -7.4dB for the entire ultra-wideband frequency range. The proposed LNA has an input reflection coefficient (S11) of less than -10dB for the ultra-wideband frequency range. It achieves input referred 1-dB compression point of 78.53dBm and input referred 3-dB compression point of 13dBm. It consumes only 24.226mW of power from a Vdd supply of 0.7V.

scholarly journals A 0.18um CMOS Low Noise Amplifier for 3-5ghz UWB Receivers

2018 ◽  
Vol 7 (3.6) ◽  
pp. 84
Author(s):  
N Malika Begum ◽  
W Yasmeen
Keyword(s):  
Power Supply ◽  
Noise Figure ◽  
Cmos Technology ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Ultra Wideband ◽  
Noise Amplifier ◽  
5 Ghz ◽  
Chebyshev Filter ◽  
Minimum Noise

This paper presents an Ultra-Wideband (UWB) 3-5 GHz Low Noise Amplifier (LNA) employing Chebyshev filter. The LNA has been designed using Cadence 0.18um CMOS technology. Proposed LNA achieves a minimum noise figure of 2.2dB, power gain of 9dB.The power consumption is 6.3mW from 1.8V power supply.  

scholarly journals CMOS Ultra-Wideband Low Noise Amplifier Design

2013 ◽  
Vol 2013 ◽  
pp. 1-6 ◽  
Author(s):  
K. Yousef ◽  
H. Jia ◽  
R. Pokharel ◽  
A. Allam ◽  
M. Ragab ◽  
...  
Keyword(s):  
Impedance Matching ◽  
Cmos Technology ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Ultra Wideband ◽  
Output Impedance ◽  
Integrated Inductor ◽  
Technology Process ◽  
Amplifier Design ◽  
Noise Amplifier

This paper presents the design of ultra-wideband low noise amplifier (UWB LNA). The proposed UWB LNA whose bandwidth extends from 2.5 GHz to 16 GHz is designed using a symmetric 3D RF integrated inductor. This UWB LNA has a gain of 11 ± 1.0 dB and a NF less than 3.3 dB. Good input and output impedance matching and good isolation are achieved over the operating frequency band. The proposed UWB LNA is driven from a 1.8 V supply. The UWB LNA is designed and simulated in standard TSMC 0.18 µm CMOS technology process.

scholarly journals Design of Low Power UWB CMOS Low Noise Amplifier using Active Inductor for WLAN Receiver

2018 ◽  
Vol 7 (2.24) ◽  
pp. 448
Author(s):  
S Manjula ◽  
M Malleshwari ◽  
M Suganthy
Keyword(s):  
Low Power ◽  
Noise Figure ◽  
Wide Band ◽  
Cmos Technology ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Design System ◽  
Active Inductor ◽  
Chip Area ◽  
Noise Amplifier

This paper presents a low power Low Noise Amplifier (LNA) using 0.18µm CMOS technology for ultra wide band (UWB) applications. gm boosting common gate (CG) LNA is designed to improve the noise performance.  For the reduction of on chip area, active inductor is employed at the input side of the designed LNA for input impedance matching. The proposed UWB LNA is designed using Advanced Design System (ADS) at UWB frequency of 3.1-10.6 GHz. Simulation results show that the gain of 10.74+ 0.01 dB, noise figure is 4.855 dB, input return loss <-13 dB and 12.5 mW power consumption.  

scholarly journals Design And Analysis Of CMOS Low Noise Amplifier Circuit For 5-GHz Cascode and Folded Cascode In 180nm Technology

2018 ◽  
Vol 7 (3) ◽  
pp. 143
Author(s):  
T. Kanthi ◽  
D. Sharath Babu Rao
Keyword(s):  
Noise Figure ◽  
Cmos Technology ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Common Source ◽  
Power Gain ◽  
Amplifier Circuit ◽  
Folded Cascode ◽  
Noise Amplifier ◽  
5 Ghz

This paper is about Low noise amplifier topologies based on 0.18µm CMOS technology. A common source stage with inductive degeneration, cascode stage and folded cascode stage is designed, simulated and the performance has been analyzed. The LNA’s are designed in 5GHz. The LNA of cascode stage of noise figure (NF) 2.044dB and power gain 4.347 is achieved. The simulations are done in cadence virtuoso spectre RF.

scholarly journals Design of Low Noise Amplifier for WLAN using pHEMT

2020 ◽  
Vol 9 (2) ◽  
pp. 272
Author(s):  
G. Thirunavukkarasu ◽  
G. Murugesan
Keyword(s):  
Noise Figure ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Low Power Consumption ◽  
Systematic Design ◽  
Noise Performance ◽  
Design And Manufacturing ◽  
Noise Amplifier ◽  
Minimum Noise ◽  
Minimum Noise Figure

The low power consumption devices are frequently focused in design and manufacturing wireless communication system. This paper gives a systematic design of a low noise amplifier for WLAN application aimed to obtain minimum noise figure. The simulation result shows that the noise figure is in the appreciable level (1.67 dB). The maximum gain is greater than 10 dB. These are the predominant requirements of an LNA. Also it posses good stability and the LNA design uses pHEMT for its appreciable noise performance.  

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