Fatigue Delamination Crack Growth of Potting Compounds in PCB/Epoxy Interfaces Under Flexure Loading

Electronics components operating under extreme thermo-mechanical stresses are often protected with underfills and potting encapsulation to isolate the severe stresses. By encapsulating the entire PCB, the resin provides complete insulation for the unit thereby combining good electrical properties with excellent mechanical protection. In military and defense applications these components are often subjected to mechanical shock loads of 50,000g and are expected to perform with reliability. Due to the bulk of material surrounding the PCB, potting and encapsulation resins are commonly two-part systems which when mixed together form a solid, fully-cured material, with no by-products. The cured potting materials are prone to interfacial delamination under dynamic shock loading which in turn potentially cause failures in the package interconnects. The study of interfacial fracture resistance in PCB/epoxy potting systems under dynamic shock loading is important in mitigating the risk of system failure in mission critical applications. In this paper, three types of epoxy potting compounds were used as an encapsulation on PCB samples. The potting compounds were selected based on their ultimate elongation under quasi-static loading. Potting compound, A is a stiffer material with 5% of ultimate elongation before failure. Potting compound, B is a moderately stiff material with 12% ultimate elongation. Finally, potting compound C is a softer material with 90% ultimate elongation before failure. The fracture properties and interfacial crack delamination of the PCB/epoxy interface were determined using three-point bend loading with a pre-crack at the interface. The fatigue crack growth of the interfacial delamination was characterized for the three epoxy systems. A prediction of number of cycles to failure and the performance of different epoxy system resistance under cyclic bending loading was assessed.

Preliminary study on geo-mechanical aspects of SSiC canisters

To meet safety requirements for underground storage of high-level nuclear waste, engineered barriers are an integral part of a modern defense-in-depth concept and therefore have to be considered in interaction with the host rock. This study presents preliminary results for the load behavior of a canister made of pressure-less sintered silicon carbide (SSiC), which forms the main retention barrier for the fission products in a new multi-layer waste package design denominated as TRIPLE C. This means a three-fold enclosure strategy, spreading the functionalities to three different ceramic barriers: first the porous potting compound surrounding each single fuel rod in the container, second the solid container wall of SSiC and third the over-pack of carbon concrete. Besides all the advantages a potential drawback of ceramics in general is their brittleness. Therefore, the behavior of SSiC structural components under static and dynamic loading has to be investigated. First results for a small model canister indicate that static loading will not create any relevant damage, even if stresses are extremely high and highly anisotropic on a canister all-around embedded. First dynamic simulations indicate that, under very unfavorable circumstances, the model canister can experience tensile stresses bigger than its tensile strength. Also, point loading may cause damage to the canister under certain conditions. Based on the performed calculations, the SSiC canister design will be optimized together with the carbon concrete over-pack, so that mechanical damage of main retention barrier can be excluded even under extreme static and dynamic conditions in a final repository.

Interfacial Delamination and Fracture Properties of Potting Compounds and PCB/Epoxy Interfaces Under Flexure Loading After Exposure to Multiple Cure Temperatures

Electronics components operating under extreme thermo-mechanical stresses are often protected with conformal coating and potting encapsulation to isolate the thermal and vibration shock loads. Development of predictive models for high-g shock survivability of electronics requires the measurement of the interface properties of the potting compounds with the printed circuit board materials. There is scarcity of interface fracture properties of porting compounds with printed circuit board materials. Potting and encapsulation resins are commonly two-part systems which when mixed together form a solid, fully cured material, with no by-products. The cured potting materials are prone to interfacial delamination under dynamic shock loading which in turn potentially cause failures in the package interconnects. The study of interfacial fracture resistance in PCB/epoxy potting systems under dynamic shock loading is important in mitigating the risk of system failure in mission critical applications. In this paper three types of epoxy potting compounds were used as an encapsulation on PCB samples. The potting compounds were selected on the basis of their ultimate elongation under quasi-static loading. Potting compound, A is stiffer material with 5% of ultimate elongation before failure. Potting compound, B is a moderately stiff material with 12% ultimate elongation. Finally potting compound C is a softer material with 90% ultimate elongation before failure. The fracture properties and interfacial crack delamination of the PCB/epoxy interface was determined using three-point bend loading with a pre-crack in the epoxy near the interface. The fracture toughness and crack initiation of the three epoxy systems was compared with the cure schedule and temperature. Fracture modeling was performed with crack tip elements in ABAQUS finite element models to determine the crack initiation and interfacial stresses. A comparison of the fracture properties and the performance of epoxy system resistance to delamination was shown through the three-point bend tests. The finite element model results were correlated with the experimental findings.

Additive Printing of Tight Tolerance Embedded Components via High Precision Shadow Masking and Their Integration with Traditional Circuit Board Manufacturing

Most embedded components manufactured today are made either by photolithography to pattern inner board layer materials or by placing discrete components on an inner board layer followed by planarization with a potting compound. These traditional methods produce devices with poor tolerance due to inherent variances in the photolithography and etch process, and parasitic capacitance of long traces. Discrete embedded components increase thickness and weight and suffer from reduced reliability caused by the planarization process. This paper introduces an alternative patterning method to integrate in-line embedded passive and active components without photolithography processing. This additive printing process uses high precision, high feature density shadow masks with micrometer-level registration. Devices are built layer by layer using off-the-shelf bulk materials instead of inks to produce tight tolerance passive and active components that can be integrated into traditional PCB and wafer-level processing. Examples of such additively manufactured devices for both DC and RF applications and preliminary test data are presented in this paper.