scholarly journals Addressing Mode and Bit Extensions to the Thumb-2 Instruction Set Architecture

2021 ◽  
Vol 5 (2) ◽  
pp. 13-17
Author(s):  
Dae-Hwan Kim
Keyword(s):  
Data Processing ◽  
Embedded Processors ◽  
Instruction Set ◽  
Instruction Set Architecture ◽  
Type Conversion ◽  
Processing Instruction ◽  
Aggregated Data ◽  
Processing Operation ◽  
Speed Up ◽  
Zero Extension

Thumb-2 is the most recent instruction set architecture for ARM processors which are one of the most widely used embedded processors. In this paper, two extensions are proposed to improve the performance of the Thumb-2 instruction set architecture, which are addressing mode extensions and sign/zero extensions combined with data processing instructions. To speed up access to an element of an aggregated data, the proposed approach first introduces three new addressing modes for load and store instructions. They are register-plus-immediate offset addressing mode, negative register offset addressing mode, and post-increment register offset addressing mode. Register-plus-immediate offset addressing mode permits two offsets and negative register offset allows offset to be a negative value of a register content. Post-increment register offset mode automatically modifies the offset address after the memory operation. The second is the sign/zero extension combined with a data processing instruction which allows the result of a data processing operation to be sign/zero extended to accelerate a type conversion. Several least frequently used instructions are reduced to provide the encoding space for the new extensions. Experiments show that the proposed approach improves performance by an average of 8.6% when compared to the Thumb-2 instruction set architecture.

An Implementation of Configurable SIMD Core on FPGA

2013 ◽  
Vol 336-338 ◽  
pp. 1925-1929
Author(s):  
Guang Wang ◽  
Yin Sheng Gao
Keyword(s):  
Wireless Communications ◽  
Data Processing ◽  
Single Instruction Multiple Data ◽  
Instruction Set ◽  
Instruction Set Architecture ◽  
Multiple Data ◽  
4G Wireless ◽  
Main Components ◽  
Computing Speed

In order to meet the computing speed required by 4G wireless communications, and to provide the different data processing widths required by different algorithms, an SIMD (Single Instruction Multiple Data) core has been designed. The ISA (Instruction Set Architecture) and main components of the SIMD core are discussed focus on how the SIMD core can be configured. Finally, the simulation result of the multiplication of two 8*8 matrices is presented to show the execution of instructions in the proposed SIMD core, and the result verifies the correctness of the SIMD core design.

scholarly journals Optimization Techniques for Verification of Out-of-Order Execution Machines

2010 ◽  
Vol 2010 ◽  
pp. 1-7
Author(s):  
Sudarshan K. Srinivasan
Keyword(s):  
Computational Complexity ◽  
Optimization Technique ◽  
Optimization Techniques ◽  
Deadlock Detection ◽  
Direct Impact ◽  
Instruction Set ◽  
Instruction Set Architecture ◽  
Speed Up ◽  
Order Execution

We develop two optimization techniques,flush-machineand collapsed flushing, to improve the efficiency of automatic refinement-abased verification of out-of-order (ooo) processor models. Refinement is a notion of equivalence that can be used to check that an ooo processor correctly implements all behaviors of its instruction set architecture (ISA), including deadlock detection. The optimization techniques work by reducing the computational complexity of the refinement map, a function central to refinement proofs that maps ooo processor model states to ISA states. This has a direct impact on the efficiency of verification, which is studied using 23 ooo processor models.Flush-machine, is a novel optimization technique. Collapsed flushing has been employed previously in the context of in-order processors. We show how to apply collapsed flushing for ooo processor models. Using both the optimizations together, we can handle 9 ooo models that could not be verified using standard flushing. Also, the optimizations provided a speed up of 23.29 over standard flushing.

scholarly journals A Review of ARM Processor Architecture History, Progress and Applications

2020 ◽  
pp. 171-179
Author(s):  
Muhammad Nabeel Asghar
Keyword(s):  
Daily Life ◽  
Embedded Processors ◽  
Instruction Set ◽  
Processor Architecture ◽  
Instruction Set Architecture ◽  
Arm Processor ◽  
The People ◽  
Efficient Processing ◽  
Embedded Chips ◽  
Architecture History

Globally, over 50 billion ARM architecture based embedded chips of 32-bit and 64-bit instruction set architecture are commonly used and produced in quantity perspective since 2014. In our daily life most of the people uses and depends upon a penalty of electrical and automotive devices which have now become an essential part of their daily life. Due to that reason embedded processors are used to build such devices which takes less silicone-space, provides efficient processing and less power.

scholarly journals Comparison of Serial and Parallel Computation on Predicting Missing Data with EM Algorithm

2021 ◽  
Vol 18 (1) ◽  
pp. 22-30
Author(s):  
Erna Nurmawati ◽  
Robby Hasan Pangaribuan ◽  
Ibnu Santoso
Keyword(s):  
Parallel Computing ◽  
Missing Data ◽  
Data Processing ◽  
Em Algorithm ◽  
Parallel Computation ◽  
Incomplete Data ◽  
Parallel Programs ◽  
Missing Value ◽  
Speed Up ◽  
Compute Time

One way to deal with the presence of missing value or incomplete data is to impute the data using EM Algorithm. The need for large and fast data processing is necessary to implement parallel computing on EM algorithm serial program. In the parallel program architecture of EM Algorithm in this study, the controller is only related to the EM module whereas the EM module itself uses matrix and vector modules intensively. Parallelization is done by using OpenMP in EM modules which results in faster compute time on parallel programs than serial programs. Parallel computing with a thread of 4 (four) increases speed up, reduces compute time, and reduces efficiency when compared to parallel computing by the number of threads 2 (two).

scholarly journals Analysis of Tools for The Description and Analytical Processing of Enviromental Data

2020 ◽  
Vol 20 (2) ◽  
pp. 129-132
Author(s):  
Vugar Abdullayev ◽  
N.A. Ragimova N.A ◽  
V.H Abdullayev ◽  
T.K Askerov
Keyword(s):  
Data Processing ◽  
Environmental Monitoring ◽  
Analytical Data ◽  
Environmental Data ◽  
Volume Data ◽  
Star Schema ◽  
Data Processing Tool ◽  
Data Volume ◽  
Speed Up ◽  
Analytical Processing

The objects of the research are tools that support the description and analytical processing of environmental data requests. These tools are used for environmental monitoring. Analytical processing of environmental data is necessary for this monitoring by the persons concerned. Here, a star schema is used to describe the data. Analytical data processing tools are required for analysis and research of environmental data. The results of analytical processing of environmental data are used to speed up decision-making. This article also describes the structure of the analytical data processing tool. Therefore, one of the problem points is how to describe the data. For this purpose, an environmental data relay scheme is defined, and the data description is implemented in multidimensional cubes. Due to the growth of data volume, data processing is carried out using multi-dimensional visualization methods. In addition, a visual user interface has been created for analytically processing queries based on scale data. The result of this research is to find a method for describing environmental data. At the end of the research, a hypercube was obtained, with the help of which it was possible to structure environmental data and carry out analytical processing of them. To this end, environmental data have been described using a multi-dimensional visualization method. And OLAP technologies were used to carry out analytical processing of this data. OLAP technologies allow aggregate data to be used and presented as a hypercube. The results of the research can be used as a basis for an environmental information system that is used for environmental monitoring.

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