Design of Low-Power Wallace Tree Multiplier Architecture Using Modular Approach

2021 ◽  
Author(s):  
Vaibhavi Solanki ◽  
A. D. Darji ◽  
Harikrishna Singapuri
Keyword(s):  
Low Power ◽  
Modular Approach ◽  
Wallace Tree ◽  
Wallace Tree Multiplier

Performance Analysis of Various Multipliers Using 8T-full Adder with 180nm Technology

2020 ◽  
Vol 13 (6) ◽  
pp. 864-870
Author(s):  
Sai Venkatramana Prasada G.S ◽  
G. Seshikala ◽  
S. Niranjana
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
High Speed ◽  
High Performance ◽  
Full Adder ◽  
Fundamental Operation ◽  
Wallace Tree ◽  
Power Delay Product ◽  
The Comparative Study ◽  
Wallace Tree Multiplier

Background: This paper presents the comparative study of power dissipation, delay and power delay product (PDP) of different full adders and multiplier designs. Methods: Full adder is the fundamental operation for any processors, DSP architectures and VLSI systems. Here ten different full adder structures were analyzed for their best performance using a Mentor Graphics tool with 180nm technology. Results: From the analysis result high performance full adder is extracted for further higher level designs. 8T full adder exhibits high speed, low power delay and low power delay product and hence it is considered to construct four different multiplier designs, such as Array multiplier, Baugh Wooley multiplier, Braun multiplier and Wallace Tree multiplier. These different structures of multipliers were designed using 8T full adder and simulated using Mentor Graphics tool in a constant W/L aspect ratio. Conclusion: From the analysis, it is concluded that Wallace Tree multiplier is the high speed multiplier but dissipates comparatively high power. Baugh Wooley multiplier dissipates less power but exhibits more time delay and low PDP.

High-performance low-power approximate Wallace tree multiplier

2018 ◽  
Vol 46 (12) ◽  
pp. 2334-2348 ◽  
Author(s):  
Sa'ed Abed ◽  
Yasser Khalil ◽  
Mahdi Modhaffar ◽  
Imtiaz Ahmad
Keyword(s):  
Low Power ◽  
High Performance ◽  
Wallace Tree ◽  
Wallace Tree Multiplier

A novel low power and high speed Wallace tree multiplier for RISC processor

2011 ◽  
Author(s):  
C. Vinoth ◽  
V. S. Kanchana Bhaaskaran ◽  
B. Brindha ◽  
S. Sakthikumaran ◽  
V. Kavinilavu ◽  
...  
Keyword(s):  
Low Power ◽  
High Speed ◽  
Wallace Tree ◽  
Risc Processor ◽  
Wallace Tree Multiplier

Modified low power Wallace Tree multiplier using higher order compressors

2016 ◽  
Vol 5 (2) ◽  
pp. 177-188 ◽  
Author(s):  
Ramanathan P. ◽  
Kowsalya P. ◽  
Anitha P.
Keyword(s):  
Low Power ◽  
Higher Order ◽  
Wallace Tree ◽  
Wallace Tree Multiplier
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