Implementation of Data Security with Wallace Tree Approach Using Elliptical Curve Cryptography on FPGA

The growth of computing resources and parallel computing has led to significant needs for efficient cryptosystems over the last decade. Elliptic Curve Cryptography (ECC) provides faster computation over other asymmetric cryptosystems such as RSA and greater security. For many cryptography operations, ECC can be used: hidden key exchange, message encryption, and digital signature. There is thus a trade-off between safety and efficiency with regard to speed, area and power requirements. This paper provides a good ECC approach to encryption by replacing the Vedic multiplier (16 bit) with the Wallace tree multiplier with an improved output (128 bit). The proposed design processes data recurringly with less volume, less power consumption and greater velocity, in addition to improving efficiency. Using Xilinx 2015.2 software, the entire proposed design is synthesized and simulated and implemented on the ZYNQ FPGA Board. Compared with previous implementations, a significant improvement in field efficiency, time complexity and energy demand is demonstrated by the proposed design.

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FPGA Implementation of 8-Bit Vedic Multiplier for DIT-FFT Application Using Urdhva Tiryagbhyam Sutra

International Journal of Advanced Research in Science, Communication and Technology ◽

10.48175/ijarsct-775 ◽

2021 ◽

pp. 156-165

Author(s):

Rohith S ◽

Kasetty Ram Babu ◽

Chandrashekar M N

Keyword(s):

Software Tool ◽

Fpga Implementation ◽

Verilog Hdl ◽

Booth Multiplier ◽

Wallace Tree ◽

Vedic Multiplier ◽

Array Multiplier ◽

Wallace Tree Multiplier

This paper discusses FPGA Implementation of 8-Bit Vedic Multiplier and DIT-FFT Application Using Urdhva Tiryagbhyam Sutra. Initially 8-bit Vedic multiplier performance is compared with existing multiplier such as i) Wallace tree multiplier ii) Array multiplier iii) Booth multiplier. In this work Urdhva Tiryagbhyam (upright and across) Vedic sutra is used for multiplier design which provides better performance and consumes smaller time for computation. In this work, Modified Carry Save Adder (MCSA) is used to compute the sum of partially generated products. Further the multiplier is It reduces the computational delay towards the addition of unfinished products. The proposed design uses the Verilog HDL to develop the algorithm. The XILINX 14.7 software tool is used to simulate and synthesize the code. The proposed design is used for DIT FFT application.

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An Efficient Design Approach of ROI Based DWT Using Vedic and Wallace Tree Multiplier on FPGA Platform

International Journal of Electrical and Computer Engineering (IJECE) ◽

10.11591/ijece.v9i4.pp2433-2442 ◽

2019 ◽

Vol 9 (4) ◽

pp. 2433

Author(s):

Vijaya SM ◽

Suresh K

Keyword(s):

Performance Metrics ◽

Brain Mri ◽

Region Of Interest ◽

Discrete Wavelet ◽

Efficient Design ◽

Pipeline Architecture ◽

Wallace Tree ◽

Vedic Multiplier ◽

Reconstruction Image ◽

Wallace Tree Multiplier

<span lang="EN-US">In digital image processing, the compression mechanism is utilized to enhance the visual perception and storage cost. By using hardware architectures, reconstruction of medical images especially Region of interest (ROI) part using Lossy image compression is a challenging task. In this paper, the ROI Based Discrete wavelet transformation (DWT) using separate Wallace- tree multiplier (WM) and modified Vedic Multiplier (VM) methods are designed. The Lifting based DWT method is used for the ROI compression and reconstruction. The 9/7 filter coefficients are multiplied in DWT using Wallace- tree multiplier (WM) and modified Vedic Multiplier (VM). The designed Wallace tree multiplier works with the parallel mechanism using pipeline architecture results with optimized hardware resources, and 8x8 Vedic multiplier designs improves the ROI reconstruction image quality and fast computation. To evaluate the performance metrics between ROI Based DWT-WM and DWT-VM on FPGA platform, The PSNR and MSE are calculated for different Brain MRI images, and also hardware constraints include Area, Delay, maximum operating frequency and power results are tabulated. The proposed model is designed using Xilinx platform using Verilog-HDL and simulated using ModelSim and Implemented on Artix-7 FPGA device.</span>

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Performance Analysis of Various Multipliers Using 8T-full Adder with 180nm Technology

Recent Advances in Electrical & Electronic Engineering (Formerly Recent Patents on Electrical & Electronic Engineering) ◽

10.2174/2352096513666200107091932 ◽

2020 ◽

Vol 13 (6) ◽

pp. 864-870

Author(s):

Sai Venkatramana Prasada G.S ◽

G. Seshikala ◽

S. Niranjana

Keyword(s):

Low Power ◽

Power Dissipation ◽

High Speed ◽

High Performance ◽

Full Adder ◽

Fundamental Operation ◽

Wallace Tree ◽

Power Delay Product ◽

The Comparative Study ◽

Wallace Tree Multiplier

Background: This paper presents the comparative study of power dissipation, delay and power delay product (PDP) of different full adders and multiplier designs. Methods: Full adder is the fundamental operation for any processors, DSP architectures and VLSI systems. Here ten different full adder structures were analyzed for their best performance using a Mentor Graphics tool with 180nm technology. Results: From the analysis result high performance full adder is extracted for further higher level designs. 8T full adder exhibits high speed, low power delay and low power delay product and hence it is considered to construct four different multiplier designs, such as Array multiplier, Baugh Wooley multiplier, Braun multiplier and Wallace Tree multiplier. These different structures of multipliers were designed using 8T full adder and simulated using Mentor Graphics tool in a constant W/L aspect ratio. Conclusion: From the analysis, it is concluded that Wallace Tree multiplier is the high speed multiplier but dissipates comparatively high power. Baugh Wooley multiplier dissipates less power but exhibits more time delay and low PDP.

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Comparative Study of Cryptography for Cloud Computing for Data Security

Recent Advances in Computer Science and Communications ◽

10.2174/2666255813666190911114909 ◽

2019 ◽

Vol 13 ◽

Author(s):

Priya Mathur ◽

Amit Kumar Gupta ◽

Prateek Vashishtha

Keyword(s):

Cloud Computing ◽

Data Security ◽

Elliptic Curve Cryptography ◽

Plain Text ◽

Hybrid Encryption ◽

Cipher Text ◽

Business Applications ◽

Computing Grid ◽

Cloud Servers ◽

Client Side

Cloud computing is an emerging technique by which anyone can access the applications as utilities over the internet. Cloud computing is the technology which comprises of all the characteristics of the technologies like distributed computing, grid computing, and ubiquitous computing. Cloud computing allows everyone to create, to configure as well as to customize the business applications online. Cryptography is the technique which is use to convert the plain text into cipher text using various encryption techniques. The art and science used to introduce the secrecy in the information security in order to secure the messages is defined as cryptography. In this paper we are going to review few latest Cryptographic algorithms which are used to enhance the security of the data on the cloud servers. We are comparing Short Range Natural Number Modified RSA (SRNN), Elliptic Curve Cryptography Algorithm, Client Side Encryption Technique and Hybrid Encryption Technique to secure the data in cloud.

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