Nowadays, most of the application depends on arithmetic designs such as an adder, multiplier, divider, etc. Among that, multipliers are very essential for designing industrial applications such as Finite Impulse Response, Fast Fourier Transform, Discrete cosine transform, etc. In the conventional methods, different kind of multipliers such as array multiplier, booth multiplier, bough Wooley multiplier, etc. are used. These existing multipliers are occupied more area to operate. In this study, Wallace Tree Multiplier (WTM) is implemented to overcome this problem. Two kinds of multipliers have designed in this research work for comparison. At first, existing WTM is designed with normal full adders and half adders. Next, proposed WTM is designed using Ladner Fischer Adder (LFA) to improve the hardware utilization and reduce the power consumption. Field Programmable Gate Array (FPGA) performances such as slice Look Up Table (LUT), Slice Register, Bonded Input-Output Bios (IOB) and power consumption are evaluated. The proposed WTM-LFA architecture occupied 374 slice LUT, 193 slice register, 59 bonded IOB, and 26.31W power. These FPGA performances are improved compared to conventional multipliers such asModified Retiming Serial Multiplier (MRSM), Digit Based Montgomery Multiplier (DBMM), and Fast Parallel Decimal Multiplier (FPDM).
Design and Estimation of delay, power and area for Parallel prefix adders
