Effects of In Situ Graphitic Nanocarbon Coatings on Cycling Performance of Silicon-Flake-Based Anode of Lithium Ion Battery

We coated graphitic nanocarbons by thermal chemical vapor deposition (CVD) on silicon flakes recycled from the waste of silicon wafer manufacturing processes as an active material for the anode of lithium ion battery (LIB). Ferrocene contains both iron catalyst and carbon, while camphor serves as an additional carbon source. Water vapor promotes catalytic growth of nanocarbons, including carbon nanotubes (CNTs), carbon fibers (CFs), and carbon films made of graphitic carbon nanoparticles, at temperatures ranging from 650 to 850 °C. The container of silicon flakes rotates for uniform coatings on silicon flakes of about 100 nm thick and 800–1000 nm in lateral dimensions. Due to short CVD time, besides CNTs and CFs, surfaces of silicon flakes deposit with high-density graphitic nanoparticles, especially at a low temperature of 650 °C. Nanocarbon coatings were characterized by SEM, EDX, ESCA, and Raman spectroscopy. Half-cells were characterized by cyclic voltammetry (CV), electrochemical impedance spectroscopy (EIS), and retention of capacity in discharge/charge cycling. Silicon-flake-based anode with nanocarbon coatings at both 650 and 850 °C exhibited capacity retention of 2000 mAh/g after 100 cycles at 0.1 C, without needing any conductivity enhancement material such as Super P.

Image Wafer Inspection based on Template Matching

This paper presents a template matching technique for detecting defects in VLSI wafer images. This method is based on traditional techniques of image analysis and image registration, but it combines the prior art of image wafer inspection in a new way, using prior knowledge like the design layout of VLSI wafer manufacturing process. This technique requires a golden template of the patterned wafer image under inspection which is obtained from the wafer image itself mixed to the layout design schemes. First a mapping between physical space and pixel space is needed. Then a template matching is applied for a more accurate alignment between wafer device and template. Finally, a segmented comparison is used for finding out possible defects. Results of the proposed method are presented in terms of visual quality of defect detection, any misalignment at topology level and number of correctly detected defective devices.