Comparative Analysis of Spintronic Memories for Low Power on-chip Caches

SPIN ◽  
2020 ◽  
Vol 10 (04) ◽  
pp. 2050027
Author(s):  
Inderjit Singh ◽  
Balwinder Raj ◽  
Mamta Khosla ◽  
Brajesh Kumar Kaushik

The continuous downscaling in CMOS devices has increased leakage power and limited the performance to a few GHz. The research goal has diverted from operating at high frequencies to deliver higher performance in essence with lower power. CMOS based on-chip memories consumes significant fraction of power in modern processors. This paper aims to explore the suitability of beyond CMOS, emerging magnetic memories for the use in memory hierarchy, attributing to their remarkable features like nonvolatility, high-density, ultra-low leakage and scalability. NVSim, a circuit-level tool, is used to explore different design layouts and memory organizations and then estimate the energy, area and latency performance numbers. A detailed system-level performance analysis of STT-MRAM and SOT-MRAM technologies and comparison with 22[Formula: see text]nm SRAM technology are presented. Analysis infers that in comparison to the existing 22[Formula: see text]nm SRAM technology, SOT-MRAM is more efficient in area for memory size [Formula: see text][Formula: see text]KB, speed and energy consumption for cache size [Formula: see text][Formula: see text]KB. A typical 256[Formula: see text]KB SOT-MRAM cache design is 27.74% area efficient, 2.97 times faster and consumes 76.05% lesser leakage than SRAM counterpart and these numbers improve for larger cache sizes. The article deduces that SOT-MRAM technology has a promising potential to replace SRAM in lower levels of computer memory hierarchy.

2013 ◽  
Vol 22 (05) ◽  
pp. 1350038 ◽  
Author(s):  
TIEFEI ZHANG ◽  
TIANZHOU CHEN ◽  
JIANZHONG WU ◽  
YOUTIAN QU

Due to its low leakage power and high density, spin torque transfer RAM (STT-RAM) has become a good candidate for future on-chip cache. However, STT-RAM suffers from higher write energy compared to the SRAM. One state-of-the-art technique to alleviate this problem is read-before-write (RBW). In this paper, we study the pattern of the write accesses to the L2 cache and show that directly applying the RBW to a STT-RAM L2 cache can be problematic from energy perspective. We then propose a selective read-before-write (SRW) scheme to further reduce the dynamic write energy of the STT-RAM cache. Additional optimizations are included in the design of SRW so that it can save a considerable amount of energy at negligible overheads. The experimental results show that SRW achieves a 86.0% reduction in write energy consumption vs. a baseline without any write optimization techniques, and a 6.55% more reduction compared to the RBW scheme.


Author(s):  
Samuel A. Howard

As gas foil journal bearings become more prevalent in production machines, such as small gas turbine propulsion systems and microturbines, system level performance issues must be identified and quantified in order to provide for successful design practices. Several examples of system level design parameters that are not fully understood in foil bearing systems are thermal management schemes, alignment requirements, balance requirements, thrust load balancing, and others. In order to address some of these deficiencies and begin to develop guidelines, this paper presents a preliminary experimental investigation of the misalignment tolerance of gas foil journal bearing systems. Using a notional gas foil bearing supported rotor and a laser-based shaft alignment system, increasing levels of misalignment are imparted to the bearing supports while monitoring temperature at the bearing edges. The amount of misalignment that induces bearing failure is identified and compared to other conventional bearing types such as cylindrical roller bearings and angular contact ball bearings. Additionally, the dynamic response of the rotor indicates that the gas foil bearing force coefficients may be affected by misalignment.


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