Design of a Digital Baseband Processor for UHF Tags

In this paper, we present a new digital baseband processor for UHF tags. It is a low-power and low-voltage digital circuit and adopts the Chinese military standard protocol GJB7377.1. The processor receives data or commands from the RF front-end and carries out various functions, such as receiving and writing data to memory, reading and sending memory data to the RF front-end and killing tags. The processor consists of thirteen main sub-modules: TPP decoding, clock management, random number generator, power management, memory controller, cyclic redundancy check, FM0 encoding, input data processing, output data processing, command detection module, initialization module, state machine module and controller. We use ModelSim for the TPP decoding simulation and communication simulation between tag and reader, and the simulation results meet the design requirements. The processor can be applied to UHF tags and has been taped out using a TSMC 0.18 um CMOS process.

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WIDEBAND ON-CHIP K-BAND RF FRONT-END FOR VEHICULAR FMCW RADAR APPLICATIONS IN 0.18 Î¼M CMOS PROCESS

Progress In Electromagnetics Research C ◽

10.2528/pierc10092203 ◽

2010 ◽

Vol 17 ◽

pp. 145-162 ◽

Cited By ~ 1

Author(s):

Han-Yeol Yu ◽

Sung-Sun Choi ◽

Yong-Hoon Kim

Keyword(s):

Cmos Process ◽

Fmcw Radar ◽

Front End ◽

Rf Front End ◽

Radar Applications ◽

On Chip ◽

K Band

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A Linearity Improvement Front End with Subharmonic Current Commutating Passive Mixer for 2.4 GHz Direct Conversion Receiver in 0.13 μm CMOS Technology

Electronics ◽

10.3390/electronics9091369 ◽

2020 ◽

Vol 9 (9) ◽

pp. 1369

Author(s):

Dongquan Huo ◽

Luhong Mao ◽

Liji Wu ◽

Xiangmin Zhang

Keyword(s):

Power Consumption ◽

Flicker Noise ◽

Analytical Formula ◽

Direct Conversion ◽

Low Noise ◽

Cmos Process ◽

Passive Mixer ◽

Dc Offset ◽

Front End ◽

Rf Front End

Direct conversion receiver (DCR) architecture is a promising candidate in the radio frequency (RF) front end because of its low power consumption, low cost and ease of integration. However, flicker noise and direct current (DC) offset are large issues. Owing to the local oscillator (LO) frequency, which is half of the RF frequency, and the absence of a DC bias current that introduces no flicker noise, the subharmonic passive mixer (SHPM) core topology front end overcomes the shortcoming effectively. When more and more receivers (RX) and transmitters (TX) are integrated into one chip, the linearity of the receiver front end becomes a very important performer that handles the TX and RX feedthrough. Another reason for the requirement of good linearity is the massive electromagnetic interference that exists in the atmosphere. This paper presents a linearity-improved RF front end with a feedforward body bias (FBB) subharmonic mixer core topology that satisfies modern RF front end demands. A novel complementary derivative superposition (DS) method is presented in low noise amplifier (LNA) design to cancel both the third- and second-order nonlinearities. To the best knowledge of the authors, this is the first time FBB technology is used in the SHPM core to improve linearity. A Volterra series is introduced to provide an analytical formula for the FBB of the SHPM core. The design was fabricated in a 0.13 μm complementary metal oxide semiconductor (CMOS) process with a chip area of 750 μm × 1270 μm. At a 2.4 GHz working frequency, the measurement result shows a conversion gain of 36 dB, double side band (DSB) noise figure (NF) of 6.8 dB, third-order intermodulation intercept point (IIP3) of 2 dBm, LO–RF isolation of 90 dB and 0.8 mW DC offset with 14.4 mW power consumption at 1.2 V supply voltage. These results exhibit better LO–RF feedthrough and DC offset, good gain and NF, moderate IIP3 and the highest figure of merit compared to the state-of-the-art publications.

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A low-voltage silicon bipolar RF front-end for PCN receiver applications

Proceedings ISSCC '95 - International Solid-State Circuits Conference ◽

10.1109/isscc.1995.535465 ◽

2002 ◽

Cited By ~ 18

Author(s):

J.R. Long ◽

M.A. Copeland ◽

P. Schvan ◽

R.A. Hadaway

Keyword(s):

Low Voltage ◽

Front End ◽

Rf Front End

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A TIME-DOMAIN 1.0-V/0.8-MW 6-BIT 125 MS/S FLASH ADC IN 65 NM CMOS

Journal of Circuits System and Computers ◽

10.1142/s0218126613500175 ◽

2013 ◽

Vol 22 (04) ◽

pp. 1350017 ◽

Cited By ~ 1

Author(s):

GUANZHONG HUANG ◽

PINGFEN LIN

Keyword(s):

Time Domain ◽

Pulse Width Modulation ◽

Low Voltage ◽

Sampling Rate ◽

Digital Signal ◽

Input Voltage ◽

Gray Code ◽

Digital Circuit ◽

Cmos Process ◽

Flash Adc

A 6-bit low-voltage power-efficient flash analog-to-digital converter (ADC) is presented in this paper. The proposed ADC replaces the conventional voltage comparator with a new approach in the time-domain. The reference voltages and the analog input voltage are converted to digital signal in a form of different pulse widths by using a pulse-width-modulation (PWM) circuit. Consequently, the comparison is achieved by checking the sequence of the pulse rising edges rather than amplifying and latching the voltage difference. The total input capacitance of the proposed ADC is as small as tens of femto-farads, resulting in much less demand for the front-end buffer and the sampling switch. In addition, an implementation of the digital foreground calibration helps to get rid of the nonmonotonic comparison thresholds due to mismatch. The calibration operates with the adaptive comparison threshold by tuning the modulation level of the PWM. The intermediate Gray code conversion increases the bubble tolerance by 1LSB. This digital-circuit-heavily-involved ADC has been designed and simulated in a 65 nm CMOS process, achieving 35.24 dB signal-to-noise-and-distortion-ratio (SNDR) at a sampling rate of 125 MS/s while consuming 803 μW from 1 V power supply. As a result, the figure of merit (FoM) is as low as 136 fJ/conversion-step.

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