GERARD: GEneral RApid Resolution of Digital Mazes Using a Memristor Emulator

Memristive technology is a promising game-changer in computers and electronics. In this paper, a system exploring the optimal paths through a maze, utilizing a memristor-based setup, is developed and concreted on a FPGA (field-programmable gate array) device. As a memristor, a digital emulator has been used. According to the proposed approach, the memristor is used as a delay element, further configuring the test graph as a memristor network. A parallel algorithm is then applied, successfully reducing computing time and increasing the system’s efficiency. The proposed system is simple, easy to scale up and capable of implementing different graph configurations. The operation of the algorithm in the MATLAB (matrix laboratory) programming enviroment is checked beforehand and then exported to two different Intel FPGAs: a DE0-Nano board and an Arria 10 GX 220 FPGA. In both cases, reliable results are obtained quickly and conveniently, even for the case of a 300 × 300 nodes maze.

A Switched Capacitor Memristor Emulator using Stochastic Computing

Due to the increased use of memristors, and its many applications, the use of emulators has grown in parallel to avoid some of the difficulties presented by real devices such as variability and reliability. In this paper, we present a memristive emulator designed using a Switched Capacitor (SC), this is, an analog component/ block and a control part or block implemented using stochastic computing (SCo) and therefore fully digital. Our design is thus a mixed signal circuit. Memristor equations are implemented using stochastic computing to generate the control signals necessary to work with the controllable resistor implemented as switched capacitor.

GERARD: GEneral RApid Resolution of Digital Mazes Using a Memristor Emulator

In this paper, a system of searching for optimal paths is developed and concreted on a FPGA. It is based on a memristive emulator, used as a delay element, by configuring the test graph as a memristor network. A parallel algorithm is applied to reduce computing time and increase efficiency. The operation of the algorithm in Matlab is checked beforehand and then exported to two different Intel FPGAs: a DE0-Nano board and an Arria 10 GX 220 FPGA. In both cases reliable results are obtained quickly and conveniently, even for the case of a 300x300 nodes maze.

Compact Charge-Controlled Memristance Simulator with Electronic/Resistive Tunability

The work endeavors to realize a single Voltage Differencing Current Conveyor (VDCC)-based current-controlled memristor emulator with charge-dependent linear memristance function. Such current-controlled memristors closely model the current ([Formula: see text])–voltage ([Formula: see text]) relationship of the popular TiO2-based physical memristor architecture constructed by Hewlett–Packard (HP). The presented emulator circuit comprises only two grounded passive elements and two external MOS transistors along with a VDCC active element and provides the facility of electronic/resistive tunability. It is found through the detailed literature survey that the presented circuit is the most compact design to realize a charge-controlled memristance simulator as compared to any previously reported structure. The designed configuration has been verified through presented simulation results generated using PSPICE based on 0.18[Formula: see text][Formula: see text]m CMOS technology. It has also been validated through relaxation and chaotic oscillators developed using the proposed VDCC-based memristor emulator and output waveforms have been shown. Furthermore, the discussed memristor emulator has been implemented and verified through commercial ICs, AD844 and LM13700.