Addressing Thermal Management Concerns for a Power Electronics Module Using an Integrated Micro-Cooling Chip Array Scheme

The field of consumer and power electronics is surging ahead with more sophisticated and powerful devices that are smaller and more capable than before. Proper and efficient thermal management of such devices is increasingly challenging when addressing requirements to reduce size, weight and cost (both manufacturing and operational) while enabling the overall system to operate at higher power densities. The current effort investigates an integrated micro-cooling chip array scheme to address the local thermal management challenges of a baseline power electronic invertor circuit. The chip array is a multi-laminate design that features localized fluidic cells ducted to bring single phase coolant in and out of a heat exchanger section. This paper focuses on a the micro-jet array scheme to address high, localized and spatially varying heat fluxes that may result from a nominal power electronics three-phase inverter module. The design approach considers manufacturability and optimization of the effective cooling performance of the micro-jet array adjacent to the power electronic module. A detailed analysis of the heat exchanger section is performed and the computational results identify the local minimum thermal resistance, the effect of increasing mass flow rate and pumping power and the achievable improvement in heat transfer with a simplistic pin array enhancement.

Theoretical Analysis and Characterization of Multi-Islands Single-Electron Devices with Applications

A two- (2D) and three-dimensional (3D) multiple-tunnel junctions array is investigated. Device structure and electrical characteristics are described. We present a comparison of carriers transport through devices based on polymetallic grains based on master equation and the orthodox theory. The Coulomb blockade effect of 2D and 3D arrays is observed at low and high temperatures. The conduction mechanism is handled by the tunnel effect, and we adopt in addition the thermionic and Fowler-Nordheim emissions. Numerical simulation results focused on flash-memory and photodetector applications. Memory characteristics such as program/erase select gate operation are demonstrated in 2D devices. Also 3D array scheme is discussed for the high-density NCs scalable for photodetector application.