Memory Characteristics of Thin Film Transistor with Catalytic Metal Layer Induced Crystallized Indium-Gallium-Zinc-Oxide (IGZO) Channel

The memory characteristics of a flash memory device using c-axis aligned crystal indium gallium zinc oxide (CAAC-IGZO) thin film as a channel material were demonstrated. The CAAC-IGZO thin films can replace the current poly-silicon channel, which has reduced mobility because of grain-induced degradation. The CAAC-IGZO thin films were achieved using a tantalum catalyst layer with annealing. A thin film transistor (TFT) with SiO2/Si3N4/Al2O3 and CAAC-IGZO thin films, where Al2O3 was used for the tunneling layer, was evaluated for a flash memory application and compared with a device using an amorphous IGZO (a-IGZO) channel. A source and drain using indium-tin oxide and aluminum were also evaluated for TFT flash memory devices with crystallized and amorphous channel materials. Compared with the a-IGZO device, higher on-current (Ion), improved field effect carrier mobility (μFE), a lower body trap (Nss), a wider memory window (ΔVth), and better retention and endurance characteristics were attained using the CAAC-IGZO device.

Photoelectroactive artificial synapse and its application to biosignal pattern recognition

In recent years, optoelectronic artificial synapses have garnered a great deal of research attention owing to their multifunctionality to process optical input signals or to update their weights optically. However, for most optoelectronic synapses, the use of optical stimuli is restricted to an excitatory spike pulse, which majorly limits their application to hardware neural networks. Here, we report a unique weight-update operation in a photoelectroactive synapse; the synaptic weight can be both potentiated and depressed using “optical spikes.” This unique bidirectional operation originates from the ionization and neutralization of inherent defects in hexagonal-boron nitride by co-stimuli consisting of optical and electrical spikes. The proposed synapse device exhibits (i) outstanding analog memory characteristics, such as high accessibility (cycle-to-cycle variation of <1%) and long retention (>21 days), and (ii) excellent synaptic dynamics, such as a high dynamic range (>384) and modest asymmetricity (<3.9). Such remarkable characteristics enable a maximum accuracy of 96.1% to be achieved during the training and inference simulation for human electrocardiogram patterns.

Modeling and Dynamics Analysis of a Universal Interface for Constructing Floating Fractional Order Mem-Elements

Fractional-order systems generalize classical differential systems and have empirically shown to achieve fine-grain modeling of the temporal dynamics and frequency responses of certain real-world phenomena. Although the study of integer-order memory element (mem-element) emulators has persisted for several years, the study of fractional-order memory elements (FOMEs) has received little attention. To promote the study of the characteristics and applications of mem-element systems in fractional calculus (FC) and memory systems, in this paper, we propose a novel universal interface for constructing floating FOMEs. When the topological structure of the interface remains unchanged, the floating fractional-order memristor (FOMR), fractional-order memcapacitor (FOMC) and fractional-order meminductor (FOMI) emulators can be realized by using the impedance combinations of different passive elements, without any mem-element emulators and mutators. When compared with previously proposed FOMEs, the proposed fractional-order mem-element emulators based on a universal interface not only feature the characteristics of floating terminals and simpler circuit structures, but can also realize all three different types of FOMEs. To explore the dynamical relationships between the mem-elements and the fractional order, we mathematically derive and analyze the maximum and minimum possible values of memductance, memcapacitance and inverse meminductance which accounts for practical design considerations when building FO systems. The memory characteristics of FOMEs are analyzed by varying their orders and stimuli frequencies. The consistency of theoretical analysis, numerical calculation and simulation results validates the correctness of our proposed emulators.

A simulation study on memory characteristics of InGaZnO-channel ferroelectric-FETs with 2D planar and 3D structure

We have investigated memory characteristics of InGaZnO (IGZO)-channel ferroelectric-FETs (FeFETs) with 2D planar and 3D structure by TCAD simulation to improve the memory window (MW) with a floating-body channel for high-density memory applications. From the study on 2D-planar FeFETs with single-gate (SG) and double-gate (DG), the MW depends on channel length (L) and enhanced with shorter L due to the stronger electrostatic coupling from the source and drain to the center region of the IGZO layer. From the study on 3D-structure FeFETs with macaroni (MAC) and nanowire (NW) structure, the large MW can be obtained especially in NW FeFETs due to the electric-field concentration by Gauss’s law in the 3D electrostatics. Furthermore, we have systematically studied and discussed the device design of MAC and NW structure FeFETs in terms of the diameter and thickness for high-density memory applications. As IGZO thickness decreases and outer diameter of the IGZO layer decreases, the MW increases due to the voltage divider and the electric-field concentration. The device parameters that can maximize the MW can be determined under the constraints of the layout and material based on this study.

Design of Synaptic Neuronal Circuit Based on Memristors

To solve the problems of poor learning efficiency and low accuracy caused by the single fixed synaptic weight in the traditional artificial neural network. On the foundation of the improved memristor model, this paper designs a synaptic neuronal circuit based on the natural memory characteristics of the memristor. This synapse is composed of six memristors. The resistance of the memristor is changed by adding a periodic square wave to update the synaptic weight. This circuit can realize signed synaptic weighting, which has certain linear characteristics. Finally, two synaptic weight update methods are proposed based on this circuit, and the validity of the design is verified through Spice simulation experiments.