Proceedings 1999 IEEE International Conference on Computer Design: VLSI in Computers and Processors (Cat. No.99CB37040)
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101

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Published By IEEE Comput. Soc

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A new development tool standard with the IEEE-ISTO

Proceedings 1999 IEEE International Conference on Computer Design: VLSI in Computers and Processors (Cat. No.99CB37040) ◽

10.1109/iccd.1999.808587 ◽

2005 ◽

Author(s):

R. Stence

Keyword(s):

Development Tool ◽

New Development

32-bit architectures for embedded systems

Proceedings 1999 IEEE International Conference on Computer Design: VLSI in Computers and Processors (Cat. No.99CB37040) ◽

10.1109/iccd.1999.808588 ◽

2005 ◽

Cited By ~ 1

Author(s):

R. Stence

Keyword(s):

Embedded Systems

On-line BIST for testing analog circuits

Proceedings 1999 IEEE International Conference on Computer Design: VLSI in Computers and Processors (Cat. No.99CB37040) ◽

10.1109/iccd.1999.808563 ◽

2003 ◽

Cited By ~ 10

Author(s):

J. Velasco-Medina ◽

I. Rayane ◽

M. Nicolaidis

Keyword(s):

Analog Circuits ◽

On Line

TriMedia CPU64 application development environment

Proceedings 1999 IEEE International Conference on Computer Design: VLSI in Computers and Processors (Cat. No.99CB37040) ◽

10.1109/iccd.1999.808602 ◽

2003 ◽

Cited By ~ 9

Author(s):

E.J.D. Pol ◽

B.J.M. Aarts ◽

J.T.J. van Eijndhoven ◽

P. Struik ◽

F.W. Sijstermans ◽

...

Keyword(s):

Application Development ◽

Development Environment

The MARCO/DARPA Gigascale Silicon Research Center

Proceedings 1999 IEEE International Conference on Computer Design: VLSI in Computers and Processors (Cat. No.99CB37040) ◽

10.1109/iccd.1999.808257 ◽

2003 ◽

Cited By ~ 4

Author(s):

K. Keutzer ◽

A.R. Newton

Keyword(s):

Research Center

High-speed CORDIC architecture based on redundant sum formation and overlapped σ-selection

Proceedings 1999 IEEE International Conference on Computer Design: VLSI in Computers and Processors (Cat. No.99CB37040) ◽

10.1109/iccd.1999.808388 ◽

2003 ◽

Author(s):

Jae Hun Choi ◽

Jae-Hyuck Kwak ◽

E.E. Swartzlander

Keyword(s):

High Speed

Decomposition of finite state machines for area, delay minimization

Proceedings 1999 IEEE International Conference on Computer Design: VLSI in Computers and Processors (Cat. No.99CB37040) ◽

10.1109/iccd.1999.808606 ◽

2003 ◽

Cited By ~ 4

Author(s):

R.S. Shelar ◽

M.P. Desai ◽

H. Narayanan

Keyword(s):

Finite State Machines ◽

State Machines ◽

Delay Minimization ◽

Finite State

Verification of scheduling in the presence of loops using uninterpreted symbolic simulation

Proceedings 1999 IEEE International Conference on Computer Design: VLSI in Computers and Processors (Cat. No.99CB37040) ◽

10.1109/iccd.1999.808581 ◽

2003 ◽

Cited By ~ 4

Author(s):

P. Ashar ◽

A. Raghunathan ◽

A. Gupta ◽

S. Bhattacharya

Keyword(s):

Symbolic Simulation

The specialization of general purpose processor architecture elements for programmable digital signal processors

Proceedings 1999 IEEE International Conference on Computer Design: VLSI in Computers and Processors (Cat. No.99CB37040) ◽

10.1109/iccd.1999.808589 ◽

2003 ◽

Author(s):

D. Steiss

Keyword(s):

Digital Signal ◽

General Purpose ◽

Digital Signal Processors ◽

Processor Architecture ◽

General Purpose Processor ◽

Signal Processors

On detecting bridges causing timing failures

Proceedings 1999 IEEE International Conference on Computer Design: VLSI in Computers and Processors (Cat. No.99CB37040) ◽

10.1109/iccd.1999.808573 ◽

2003 ◽

Cited By ~ 6

Author(s):

S. Mandava ◽

S. Chakravarty ◽

S. Kundu

Proceedings 1999 IEEE International Conference on Computer Design: VLSI in Computers and Processors (Cat. No.99CB37040)Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE Comput. Soc

A new development tool standard with the IEEE-ISTO

32-bit architectures for embedded systems

On-line BIST for testing analog circuits

TriMedia CPU64 application development environment

The MARCO/DARPA Gigascale Silicon Research Center

High-speed CORDIC architecture based on redundant sum formation and overlapped σ-selection

Decomposition of finite state machines for area, delay minimization

Verification of scheduling in the presence of loops using uninterpreted symbolic simulation

The specialization of general purpose processor architecture elements for programmable digital signal processors

On detecting bridges causing timing failures

Proceedings 1999 IEEE International Conference on Computer Design: VLSI in Computers and Processors (Cat. No.99CB37040)
Latest Publications