Proceedings 1999 IEEE International Conference on Computer Design: VLSI in Computers and Processors (Cat. No.99CB37040)
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A new development tool standard with the IEEE-ISTO

Proceedings 1999 IEEE International Conference on Computer Design: VLSI in Computers and Processors (Cat. No.99CB37040) ◽

10.1109/iccd.1999.808587 ◽

2005 ◽

Author(s):

R. Stence

Keyword(s):

Development Tool ◽

New Development

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32-bit architectures for embedded systems

Proceedings 1999 IEEE International Conference on Computer Design: VLSI in Computers and Processors (Cat. No.99CB37040) ◽

10.1109/iccd.1999.808588 ◽

2005 ◽

Author(s):

R. Stence

Keyword(s):

Embedded Systems

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The MARCO/DARPA Gigascale Silicon Research Center

Proceedings 1999 IEEE International Conference on Computer Design: VLSI in Computers and Processors (Cat. No.99CB37040) ◽

10.1109/iccd.1999.808257 ◽

2003 ◽

Author(s):

K. Keutzer ◽

A.R. Newton

Keyword(s):

Research Center

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On-line BIST for testing analog circuits

Proceedings 1999 IEEE International Conference on Computer Design: VLSI in Computers and Processors (Cat. No.99CB37040) ◽

10.1109/iccd.1999.808563 ◽

2003 ◽

Author(s):

J. Velasco-Medina ◽

I. Rayane ◽

M. Nicolaidis

Keyword(s):

Analog Circuits ◽

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TriMedia CPU64 application development environment

Proceedings 1999 IEEE International Conference on Computer Design: VLSI in Computers and Processors (Cat. No.99CB37040) ◽

10.1109/iccd.1999.808602 ◽

2003 ◽

Author(s):

E.J.D. Pol ◽

B.J.M. Aarts ◽

J.T.J. van Eijndhoven ◽

P. Struik ◽

F.W. Sijstermans ◽

...

Keyword(s):

Application Development ◽

Development Environment

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Decomposition of finite state machines for area, delay minimization

Proceedings 1999 IEEE International Conference on Computer Design: VLSI in Computers and Processors (Cat. No.99CB37040) ◽

10.1109/iccd.1999.808606 ◽

2003 ◽

Author(s):

R.S. Shelar ◽

M.P. Desai ◽

H. Narayanan

Keyword(s):

Finite State Machines ◽

State Machines ◽

Delay Minimization ◽

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High-speed CORDIC architecture based on redundant sum formation and overlapped σ-selection

Proceedings 1999 IEEE International Conference on Computer Design: VLSI in Computers and Processors (Cat. No.99CB37040) ◽

10.1109/iccd.1999.808388 ◽

2003 ◽

Author(s):

Jae Hun Choi ◽

Jae-Hyuck Kwak ◽

E.E. Swartzlander

Keyword(s):

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Verification of scheduling in the presence of loops using uninterpreted symbolic simulation

Proceedings 1999 IEEE International Conference on Computer Design: VLSI in Computers and Processors (Cat. No.99CB37040) ◽

10.1109/iccd.1999.808581 ◽

2003 ◽

Author(s):

P. Ashar ◽

A. Raghunathan ◽

A. Gupta ◽

S. Bhattacharya

Keyword(s):

Symbolic Simulation

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The specialization of general purpose processor architecture elements for programmable digital signal processors

Proceedings 1999 IEEE International Conference on Computer Design: VLSI in Computers and Processors (Cat. No.99CB37040) ◽

10.1109/iccd.1999.808589 ◽

2003 ◽

Author(s):

D. Steiss

Keyword(s):

Digital Signal ◽

General Purpose ◽

Digital Signal Processors ◽

Processor Architecture ◽

General Purpose Processor ◽

Signal Processors

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On detecting bridges causing timing failures

Proceedings 1999 IEEE International Conference on Computer Design: VLSI in Computers and Processors (Cat. No.99CB37040) ◽

10.1109/iccd.1999.808573 ◽

2003 ◽

Author(s):

S. Mandava ◽

S. Chakravarty ◽

S. Kundu

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