ESSCIRC 2008 - 34th European Solid-State Circuits Conference
Latest Publications

TOTAL DOCUMENTS

133

(FIVE YEARS 0)

H-INDEX

(FIVE YEARS 0)

Published By IEEE

9781424423613

Latest Documents Most Cited Documents Contributed Authors Related Sources Related Keywords

Current reuse CMOS LNA for UWB applications

ESSCIRC 2008 - 34th European Solid-State Circuits Conference ◽

10.1109/esscirc.2008.4681850 ◽

2008 ◽

Cited By ~ 9

Author(s):

T. Taris ◽

Y. Deval ◽

J.B. Begueret

Keyword(s):

Current Reuse ◽

Cmos Lna ◽

Uwb Applications

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A 11 mW 68dB SFDR 100 MHz bandwidth ΔΣ-DAC based on a 5-bit 1GS/s core in 130nm

ESSCIRC 2008 - 34th European Solid-State Circuits Conference ◽

10.1109/esscirc.2008.4681830 ◽

2008 ◽

Cited By ~ 5

Author(s):

Pieter Palmers ◽

Michiel Steyaert

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An adaptive 4-tap analog FIR equalizer for 10-Gb/s over backplane serial link receiver

ESSCIRC 2008 - 34th European Solid-State Circuits Conference ◽

10.1109/esscirc.2008.4681821 ◽

2008 ◽

Author(s):

Ori Eshet ◽

Adee Ran ◽

Amir Mezer ◽

Yaniv Hadar ◽

Dror Lazar ◽

...

Keyword(s):

Serial Link

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A low-complexity, low phase noise, low-voltage phase-aligned ring oscillator in 90 nm digital CMOS

ESSCIRC 2008 - 34th European Solid-State Circuits Conference ◽

10.1109/esscirc.2008.4681879 ◽

2008 ◽

Cited By ~ 4

Author(s):

J. Borremans ◽

J. Ryckaert ◽

P. Wambacq ◽

M. Kuijk ◽

J. Craninckx

Keyword(s):

Phase Noise ◽

Low Voltage ◽

Low Complexity ◽

Ring Oscillator ◽

Digital Cmos ◽

Voltage Phase ◽

Low Phase Noise

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Low drop-out voltage regulator with full on-chip capacitance for slot-based operation

ESSCIRC 2008 - 34th European Solid-State Circuits Conference ◽

10.1109/esscirc.2008.4681863 ◽

2008 ◽

Cited By ~ 16

Author(s):

Wim Kruiskamp ◽

Rene Beumer

Keyword(s):

Drop Out ◽

Voltage Regulator ◽

On Chip

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A low-power programmable dynamic frequency divider

ESSCIRC 2008 - 34th European Solid-State Circuits Conference ◽

10.1109/esscirc.2008.4681869 ◽

2008 ◽

Cited By ~ 6

Author(s):

Jeremie Chabloz ◽

David Ruffieux ◽

Christian Enz

Keyword(s):

Low Power ◽

Frequency Divider ◽

Dynamic Frequency

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A 3.6pJ/access 480MHz, 128Kbit on-Chip SRAM with 850MHz boost mode in 90nm CMOS with tunable sense amplifiers to cope with variability

ESSCIRC 2008 - 34th European Solid-State Circuits Conference ◽

10.1109/esscirc.2008.4681846 ◽

2008 ◽

Cited By ~ 18

Author(s):

Stefan Cosemans ◽

Wim Dehaene ◽

Francky Catthoor

Keyword(s):

Sense Amplifiers ◽

On Chip

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A fractional spur reduction technique for RF TDC-based all digital PLLs

ESSCIRC 2008 - 34th European Solid-State Circuits Conference ◽

10.1109/esscirc.2008.4681882 ◽

2008 ◽

Cited By ~ 3

Author(s):

Ping-Ying Wang ◽

Hsiang-Hui Chang ◽

Jing-Hong Conan Zhan

Keyword(s):

Reduction Technique

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A 5.2Gb/p/s GDDR5 SDRAM with CML clock distribution network

ESSCIRC 2008 - 34th European Solid-State Circuits Conference ◽

10.1109/esscirc.2008.4681825 ◽

2008 ◽

Author(s):

KyungHoon Kim ◽

SangSic Yoon ◽

KiChang Kwean ◽

DaeHan Kwon ◽

SunSuk Yang ◽

...

Keyword(s):

Distribution Network ◽

Clock Distribution ◽

Clock Distribution Network

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A 1.2V receiver front-end for multi-standard wireless applications in 65 nm CMOS LP

ESSCIRC 2008 - 34th European Solid-State Circuits Conference ◽

10.1109/esscirc.2008.4681880 ◽

2008 ◽

Author(s):

M. Vidojkovic ◽

M.A.T. Sanduleanu ◽

V. Vidojkovic ◽

J. van der Tang ◽

P. Baltus ◽

...

Keyword(s):

Wireless Applications ◽

Front End

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ESSCIRC 2008 - 34th European Solid-State Circuits ConferenceLatest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

Current reuse CMOS LNA for UWB applications

A 11 mW 68dB SFDR 100 MHz bandwidth ΔΣ-DAC based on a 5-bit 1GS/s core in 130nm

An adaptive 4-tap analog FIR equalizer for 10-Gb/s over backplane serial link receiver

A low-complexity, low phase noise, low-voltage phase-aligned ring oscillator in 90 nm digital CMOS

Low drop-out voltage regulator with full on-chip capacitance for slot-based operation

A low-power programmable dynamic frequency divider

A 3.6pJ/access 480MHz, 128Kbit on-Chip SRAM with 850MHz boost mode in 90nm CMOS with tunable sense amplifiers to cope with variability

A fractional spur reduction technique for RF TDC-based all digital PLLs

A 5.2Gb/p/s GDDR5 SDRAM with CML clock distribution network

A 1.2V receiver front-end for multi-standard wireless applications in 65 nm CMOS LP

ESSCIRC 2008 - 34th European Solid-State Circuits Conference
Latest Publications