A low-complexity, low phase noise, low-voltage phase-aligned ring oscillator in 90 nm digital CMOS

2008 ◽  
Author(s):  
J. Borremans ◽  
J. Ryckaert ◽  
P. Wambacq ◽  
M. Kuijk ◽  
J. Craninckx
Keyword(s):  
Phase Noise ◽  
Low Voltage ◽  
Low Complexity ◽  
Ring Oscillator ◽  
Digital Cmos ◽  
Voltage Phase ◽  
Low Phase Noise

A Low-Complexity, Low-Phase-Noise, Low-Voltage Phase-Aligned Ring Oscillator in 90 nm Digital CMOS

2009 ◽  
Vol 44 (7) ◽  
pp. 1942-1949 ◽  
Author(s):  
Jonathan Borremans ◽  
Julien Ryckaert ◽  
Claude Desset ◽  
Maarten Kuijk ◽  
Piet Wambacq ◽  
...  
Keyword(s):  
Phase Noise ◽  
Low Voltage ◽  
Low Complexity ◽  
Ring Oscillator ◽  
Digital Cmos ◽  
Voltage Phase ◽  
Low Phase Noise

Power Efficient Implementation of Low Noise CMOS LC VCO using 32nm Technology for RF Applications

2018 ◽  
Vol 6 (8) ◽  
pp. 53
Author(s):  
Shitesh Tiwari ◽  
Sumant Katiyal ◽  
Parag Parandkar
Keyword(s):  
Power Consumption ◽  
Phase Noise ◽  
Tuning Range ◽  
Low Voltage ◽  
Performance Comparison ◽  
Low Noise ◽  
Center Frequency ◽  
Voltage Controlled Oscillator ◽  
Low Phase Noise ◽  
Lc Vco

Voltage Controlled Oscillator (VCO) is an integral component of most of the receivers such as GSM, GPS etc. As name indicates, oscillation is controlled by varying the voltage at the capacitor of LC tank. By varying the voltage, VCO can generate variable frequency of oscillation. Different VCO Parameters are contrasted on the basis of phase noise, tuning range, power consumption and FOM. Out of these phase noise is dependent on quality factor, power consumption, oscillation frequency and current. So, design of LC VCO at low power, low phase noise can be obtained with low bias current at low voltage.  Nanosize transistors are also contributes towards low phase noise. This paper demonstrates the design of low phase noise LC VCO with 4.89 GHz tuning range from 7.33-11.22 GHz with center frequency at 7 GHz. The design uses 32nm technology with tuning voltage of 0-1.2 V. A very effective Phase noise of -114 dBc / Hz is obtained with FOM of -181 dBc/Hz. The proposed work has been compared with five peer LC VCO designs working at higher feature sizes and outcome of this performance comparison dictates that the proposed work working at better 32 nm technology outperformed amongst others in terms of achieving low Tuning voltage and moderate FoM, overshadowed by a little expense of power dissipation. 

A low-phase-noise ring oscillator with coarse and fine tuning in a standard CMOS process

2012 ◽  
Vol 33 (7) ◽  
pp. 075004 ◽  
Author(s):  
Haijun Gao ◽  
Lingling Sun ◽  
Xiaofei Kuang ◽  
Liheng Lou
Keyword(s):  
Phase Noise ◽  
Fine Tuning ◽  
Ring Oscillator ◽  
Cmos Process ◽  
Standard Cmos Process ◽  
Low Phase Noise

scholarly journals Design of Low Power and Low Phase Noise Current Starved Ring Oscillator for RFID Tag EEPROM

2019 ◽  
pp. 19-23
Keyword(s):  
Low Power ◽  
Phase Noise ◽  
Power Dissipation ◽  
Supply Voltage ◽  
Ring Oscillator ◽  
Cmos Process ◽  
Clock Signal ◽  
Voltage Level ◽  
Rfid Tag ◽  
Low Phase Noise

Power dissipation of CMOS IC is a key factor in low power applications especially in RFID tag memories. Generally, tag memories like electrically erasable programmable read-only memory (EEPROM) require an internal clock generator to regulate the internal voltage level properly. In EEPROM, oscillator circuit can generate any periodic clock signal for frequency translation. Among different types of oscillators, a current starved ring oscillator (CSRO) is described in this research due to its very low current biasing source, which in turn restrict the current flows to reduce the overall power dissipation. The designed CSRO is limited to three stages to reduce the power dissipation to meet the specs. The simulated output shows that, the improved CSRO dissipates only 4.9 mW under the power supply voltage (VDD) 1.2 V in Silterra 130 nm CMOS process. Moreover, this designed oscillator has the lowest phase noise -119.38 dBc/Hz compared to other research works. In addition, the designed CSRO is able to reduce the overall chip area, which is only 0.00114 mm2. Therefore, this proposed low power and low phase noise CSRO will be able to regulate the voltage level successfully for low power RFID tag EEPROM.

scholarly journals A New Phase-Locked Loop with Active Inductor Ring Oscillator

2021 ◽  
Author(s):  
Mohamad El-Hage
Keyword(s):  
Phase Noise ◽  
High Speed ◽  
Low Voltage ◽  
Building Blocks ◽  
Phase Locked Loop ◽  
Timing Jitter ◽  
Ring Oscillator ◽  
Control Voltage ◽  
Active Inductor ◽  
Switching Noise

Many of today's applications require that a phase-locked loop (PLL) operate at high speeds, while maintaining reasonable phase noise and jitter performance. Voltage-controlled oscillators (VCO) are important building blocks in PLLs. More importantly, the VCO is the major contributor of phase noise in a PLL. The noisy environment, mainly due to the switching noise generated by the digital portion of these systems. imposes stringent constraints on the design of VCOs, especially phase noise or timing jitter. The switching noise originated in the digital portion of the systems are coupled to the supply and ground rails of the VCO of PLLs. Another important block of a PLL is the charge-pump, a block that is responsible for generating the control voltage to be applied to the VCO. The stability or fluctuation of the control voltage, can severely affect the phase noise performance of the VCO. The research in this thesis, centered on (i) the design considerations of CMOS charge-pumps, (ii) the timing jitter of the delay-cells of low-voltage CMOS ring-VCOs and (iii) the design of a high-speed ring oscillator. A PLL was designed using a new active inductor 6.3-GHz ring oscillator, with a tuning range of +/- 15% was designed in 0.18um CMOS technology. The ring oscillator employed active inductor loads that resulted in an improvement of about 42% in oscillation frequency when compared to the conventional resistor loaded ring oscillator.

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