Proceedings IEEE Computer Society Workshop on VLSI'98 System Level Design (Cat. No.98EX158)
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Published By IEEE Comput. Soc

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Mixed signal portable wireless packaging design and test challenges

Proceedings IEEE Computer Society Workshop on VLSI'98 System Level Design (Cat. No.98EX158) ◽

10.1109/iwv.1998.667124 ◽

2002 ◽

Cited By ~ 1

Author(s):

M. Swaminathan ◽

S. Pannala

Keyword(s):

Mixed Signal ◽

Packaging Design

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IFSys: an integrated framework for system-level synthesis

Proceedings IEEE Computer Society Workshop on VLSI'98 System Level Design (Cat. No.98EX158) ◽

10.1109/iwv.1998.667106 ◽

2002 ◽

Author(s):

J. Deang ◽

G. McNally ◽

D. Siewiorek

Keyword(s):

System Level ◽

Integrated Framework

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Power-efficient data storage and transfer methodologies: Current solutions and remaining problems

Proceedings IEEE Computer Society Workshop on VLSI'98 System Level Design (Cat. No.98EX158) ◽

10.1109/iwv.1998.667115 ◽

2002 ◽

Cited By ~ 2

Author(s):

F. Catthoor

Keyword(s):

Data Storage ◽

Power Efficient ◽

Efficient Data

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Instruction subsetting: Trading power for programmability

Proceedings IEEE Computer Society Workshop on VLSI'98 System Level Design (Cat. No.98EX158) ◽

10.1109/iwv.1998.667112 ◽

2002 ◽

Cited By ~ 8

Author(s):

W.E. Dougherty ◽

D.J. Pursley ◽

D.E. Thomas

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Timing issues in system-level design

Proceedings IEEE Computer Society Workshop on VLSI'98 System Level Design (Cat. No.98EX158) ◽

10.1109/iwv.1998.667136 ◽

2002 ◽

Cited By ~ 3

Author(s):

A. Dasdan ◽

R.K. Gupta

Keyword(s):

System Level ◽

System Level Design ◽

Level Design

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A design methodology for highly-integrated wireless communications systems

Proceedings IEEE Computer Society Workshop on VLSI'98 System Level Design (Cat. No.98EX158) ◽

10.1109/iwv.1998.667118 ◽

2002 ◽

Cited By ~ 1

Author(s):

T.E. Truman ◽

R.W. Brodersen

Keyword(s):

Wireless Communications ◽

Design Methodology ◽

Communications Systems ◽

Wireless Communications Systems

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System level design as applied to CMU wearable computers

Proceedings IEEE Computer Society Workshop on VLSI'98 System Level Design (Cat. No.98EX158) ◽

10.1109/iwv.1998.667123 ◽

2002 ◽

Cited By ~ 3

Author(s):

A. Smailagic ◽

D. Siewiorek

Keyword(s):

System Level ◽

System Level Design ◽

Wearable Computers ◽

Level Design

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Experiences with system level design for consumer ICs

Proceedings IEEE Computer Society Workshop on VLSI'98 System Level Design (Cat. No.98EX158) ◽

10.1109/iwv.1998.667108 ◽

2002 ◽

Cited By ~ 3

Author(s):

J. van Meerbergen ◽

A. Timmer ◽

J. Leijten ◽

F. Harmsze ◽

M. Strik

Keyword(s):

System Level ◽

System Level Design ◽

Level Design

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A 32 Kbs on-chip memory with high port-multiplicity (5 reads and 2 writes) for effective implementation of shared memory systems

Proceedings IEEE Computer Society Workshop on VLSI'98 System Level Design (Cat. No.98EX158) ◽

10.1109/iwv.1998.667139 ◽

2002 ◽

Author(s):

T. Tsang ◽

Ching Li ◽

M. Kalluri

Keyword(s):

Shared Memory ◽

Memory Systems ◽

Effective Implementation ◽

On Chip

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Matisse: a system-on-chip design methodology emphasizing dynamic memory management

Proceedings IEEE Computer Society Workshop on VLSI'98 System Level Design (Cat. No.98EX158) ◽

10.1109/iwv.1998.667133 ◽

2002 ◽

Cited By ~ 9

Author(s):

D. Verkest ◽

J. Leao da Silva ◽

C. Ykman ◽

K. Croes ◽

M. Miranda ◽

...

Keyword(s):

Memory Management ◽

Design Methodology ◽

System On Chip ◽

Chip Design ◽

Dynamic Memory ◽

Dynamic Memory Management ◽

On Chip

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Proceedings IEEE Computer Society Workshop on VLSI'98 System Level Design (Cat. No.98EX158)Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE Comput. Soc

Mixed signal portable wireless packaging design and test challenges

IFSys: an integrated framework for system-level synthesis

Power-efficient data storage and transfer methodologies: Current solutions and remaining problems

Instruction subsetting: Trading power for programmability

Timing issues in system-level design

A design methodology for highly-integrated wireless communications systems

System level design as applied to CMU wearable computers

Experiences with system level design for consumer ICs

A 32 Kbs on-chip memory with high port-multiplicity (5 reads and 2 writes) for effective implementation of shared memory systems

Matisse: a system-on-chip design methodology emphasizing dynamic memory management

Proceedings IEEE Computer Society Workshop on VLSI'98 System Level Design (Cat. No.98EX158)
Latest Publications