Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004.
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A 0.602 /spl mu/m/sup 2/ nestled 'Chain' cell structure formed by one mask etching process for 64 Mbit FeRAM

2004 ◽  
Author(s):  
H. Kanaya ◽  
K. Tomioka ◽  
T. Matsushita ◽  
M. Omura ◽  
T. Ozaki ◽  
...  
Keyword(s):  
Cell Structure ◽  
Etching Process ◽  
Mask Etching

35% drive current improvement from recessed-SiGe drain extensions on 37 nm gate length PMOS

2004 ◽  
Author(s):  
P.R. Chidambaram ◽  
B.A. Smith ◽  
L.H. Hall ◽  
H. Bu ◽  
S. Chakravarthi ◽  
...  
Keyword(s):  
Gate Length ◽  
Drive Current

Dielectric breakdown mechanism of HfSiON/SiO/sub 2/ gate dielectric

2004 ◽  
Author(s):  
K. Torii ◽  
T. Aoyama ◽  
S. Kamiyama ◽  
Y. Tamura ◽  
S. Miyazaki ◽  
...  
Keyword(s):  
Gate Dielectric ◽  
Dielectric Breakdown ◽  
Breakdown Mechanism

45nm CMOS platform technology (CMOS6) with high density embedded memories

2004 ◽  
Author(s):  
M. Iwai ◽  
A. Oishi ◽  
T. Sanuki ◽  
Y. Takegawa ◽  
T. Komoda ◽  
...  
Keyword(s):  
High Density ◽  
Platform Technology ◽  
Embedded Memories

A 65nm-node LSTP (Low standby power) poly-Si/a-Si/HfSiON transistor with high I/sub on/-I/sub standby/ ratio and reliability

2004 ◽  
Author(s):  
Y. Yasuda ◽  
N. Kimizuka ◽  
T. Iwamoto ◽  
S. Fujieda ◽  
T. Ogura ◽  
...  
Keyword(s):  
Standby Power
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