45nm CMOS platform technology (CMOS6) with high density embedded memories

Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004. ◽

10.1109/vlsit.2004.1345364 ◽

2004 ◽

Author(s):

M. Iwai ◽

A. Oishi ◽

T. Sanuki ◽

Y. Takegawa ◽

T. Komoda ◽

...

Keyword(s):

High Density ◽

Platform Technology ◽

Embedded Memories

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A 32nm SoC platform technology with 2nd generation high-k/metal gate transistors optimized for ultra low power, high performance, and high density product applications

2009 IEEE International Electron Devices Meeting (IEDM) ◽

10.1109/iedm.2009.5424258 ◽

2009 ◽

Author(s):

C.-H. Jan ◽

M. Agostinelli ◽

M. Buehler ◽

Z.-P. Chen ◽

S.-J. Choi ◽

...

Keyword(s):

Low Power ◽

High Performance ◽

High Density ◽

Ultra Low Power ◽

High K ◽

Platform Technology

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A 22nm SoC platform technology featuring 3-D tri-gate and high-k/metal gate, optimized for ultra low power, high performance and high density SoC applications

2012 International Electron Devices Meeting ◽

10.1109/iedm.2012.6478969 ◽

2012 ◽

Author(s):

C.-H. Jan ◽

U. Bhattacharya ◽

R. Brain ◽

S.-J. Choi ◽

G. Curello ◽

...

Keyword(s):

Low Power ◽

High Performance ◽

High Density ◽

Ultra Low Power ◽

High K ◽

Platform Technology

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A capacitor-less DRAM cell on 75nm gate length, 16nm thin fully depleted SOI device for high density embedded memories

IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004. ◽

10.1109/iedm.2004.1419131 ◽

2005 ◽

Author(s):

R. Ranica ◽

A. Villaret ◽

C. Fenouillet-Beranger ◽

P. Malinge ◽

P. Mazoyer ◽

...

Keyword(s):

High Density ◽

Gate Length ◽

Fully Depleted ◽

Embedded Memories

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A 14 nm SoC platform technology featuring 2nd generation Tri-Gate transistors, 70 nm gate pitch, 52 nm metal pitch, and 0.0499 um2 SRAM cells, optimized for low power, high performance and high density SoC products

2015 Symposium on VLSI Circuits (VLSI Circuits) ◽

10.1109/vlsic.2015.7231380 ◽

2015 ◽

Author(s):

C.-H. Jan ◽

F. Al-amoody ◽

H.-Y. Chang ◽

T. Chang ◽

Y.-W. Chen ◽

...

Keyword(s):

Low Power ◽

High Performance ◽

High Density ◽

Platform Technology

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A 32nm CMOS Low Power SoC Platform Technology for Foundry Applications with Functional High Density SRAM

2007 IEEE International Electron Devices Meeting ◽

10.1109/iedm.2007.4418918 ◽

2007 ◽

Author(s):

Shien-Yang Wu ◽

C.W. Chou ◽

C.Y. Lin ◽

M.C. Chiang ◽

C.K. Yang ◽

...

Keyword(s):

Low Power ◽

High Density ◽

Platform Technology

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A 7nm CMOS platform technology featuring 4th generation FinFET transistors with a 0.027um2 high density 6-T SRAM cell for mobile SoC applications

2016 IEEE International Electron Devices Meeting (IEDM) ◽

10.1109/iedm.2016.7838333 ◽

2016 ◽

Author(s):

Shien-Yang Wu ◽

C.Y. Lin ◽

M.C. Chiang ◽

J.J. Liaw ◽

J.Y. Cheng ◽

...

Keyword(s):

High Density ◽

Sram Cell ◽

Platform Technology ◽

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Reliability studies of a 22nm SoC platform technology featuring 3-D tri-gate, optimized for ultra low power, high performance and high density application

2013 IEEE International Reliability Physics Symposium (IRPS) ◽

10.1109/irps.2013.6532105 ◽

2013 ◽

Author(s):

A. Rahman ◽

P. Bai ◽

G. Curello ◽

J. Hicks ◽

C.-H Jan ◽

...

Keyword(s):

Low Power ◽

High Performance ◽

High Density ◽

Ultra Low Power ◽

Platform Technology

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A 14 nm SoC platform technology featuring 2nd generation Tri-Gate transistors, 70 nm gate pitch, 52 nm metal pitch, and 0.0499 um2 SRAM cells, optimized for low power, high performance and high density SoC products

2015 Symposium on VLSI Technology (VLSI Technology) ◽

10.1109/vlsit.2015.7223683 ◽

2015 ◽

Author(s):

C.-H. Jan ◽

F. Al-amoody ◽

H.-Y. Chang ◽

T. Chang ◽

Y.-W. Chen ◽

...

Keyword(s):

Low Power ◽

High Performance ◽

High Density ◽

Platform Technology

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ArF lithography technologies for 65 nm-node CMOS (CMOS5) with 30 nm logic gate and high density embedded memories

2003 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.03CH37407) ◽

10.1109/vlsit.2003.1221078 ◽

2004 ◽

Author(s):

K. Hashimoto ◽

F. Uesawa ◽

K. Takahata ◽

K. Kikuchi ◽

H. Kanai ◽

...

Keyword(s):

High Density ◽

Embedded Memories

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65 nm CMOS technology (CMOS5) with high density embedded memories for broadband microprocessor applications

Digest. International Electron Devices Meeting, ◽

10.1109/iedm.2002.1175778 ◽

2003 ◽

Author(s):

N. Yanagiya ◽

S. Matsuda ◽

S. Inaba ◽

M. Takayanagi ◽

I. Mizushima ◽

...

Keyword(s):

Cmos Technology ◽

High Density ◽

Embedded Memories

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