This paper introduces a device performance optimization approach for the FinFET through optimization of the gate length. As a result of reducing the gate length, the leakage current (I[Formula: see text]) increases, and consequently, the stress along the channel enhances which leads to an increase in the drive current (I[Formula: see text]) of the PMOS. In order to sustain I[Formula: see text], work function is adjusted to offset the effect of the increased stress. Changing the gate length of the transistor yields different drive currents when the leakage current is fixed by adjusting the work function. For a given device, an optimal gate length is found to provide the highest drive current. As an example, for a standard performance device with I[Formula: see text] = 1 nA/um, the best performance I[Formula: see text] = 856 uA/um is at L = 34 nm for 14 nm FinFET and I[Formula: see text] = 1130 uA/um at L = 21 nm for 7 nm FinFET. A 7 nm FinFET will exhibit performance boost of 32% comparing with 14 nm FinFET. However, applying the same method to a 5 nm FinFET, the performance boosting is out of expectance comparing to the 7 nm FinFET, which is due to the severe short-channel-effect and the exhausted channel stress in the FinFET.
Ab initio perspective of ultra-scaled CMOS from 2D-material fundamentals to dynamically doped transistors
