Towards practical quantum computers: transmon qubit with a lifetime approaching 0.5 milliseconds

Here we report a breakthrough in the fabrication of a long lifetime transmon qubit. We use tantalum films as the base superconductor. By using a dry etching process, we obtained transmon qubits with a best T1 lifetime of 503 μs. As a comparison, we also fabricated transmon qubits with other popular materials, including niobium and aluminum, under the same design and fabrication processes. After characterizing their coherence properties, we found that qubits prepared with tantalum films have the best performance. Since the dry etching process is stable and highly anisotropic, it is much more suitable for fabricating complex scalable quantum circuits, when compared to wet etching. As a result, the current breakthrough indicates that the dry etching process of tantalum film is a promising approach to fabricate medium- or large-scale superconducting quantum circuits with a much longer lifetime, meeting the requirements for building practical quantum computers.

Competitive effect between roughness and mask pattern on charging phenomena during plasma etching

In plasma etching process, the edge roughness and mask pattern usually play a significant role in the deformation of holes under the influence of charging effect. The competitive effect between these two factors has been investigated, focusing on the surface charging in a hexagonal array, with various values of roughness parameters (amplitude (A) and wavelength (W)) and distances between holes (L). A series of classical particle dynamic simulations of surface charging, surface etching and profile evolution were used to investigate the effect of roughness and pattern on charging. This study showed that various roughness and patterns (represented by different values of L) can significantly influence surface distributions of the electric-field (E-field) and the etching rates on the mask surface. The simulations also showed that (1) the shape of the pattern array influences the mask hole profile during etching process, i.e. a hexagonal array pattern tends to deform the profile of a circular mask hole into a hexagonal hole; (2) pattern roughness is aggravated during etching process. These factors were found to be significant only at a small feature pitch and may be ignored at a large feature pitch. Possible mechanisms of these results during etching process are discussed. This work sheds light on the ways to maintain pattern integrity and further improve the quality of the pattern transfer onto the substrate.

500℃ high-temperature reliability of Ni/Nb Ohmic contact on n-type 4H-SiC

The reliability of Ni/Nb ohmic contact on n-type 4H-SiC at 500℃ was investigated. The current-voltage characteristics showed that, while the Ni(50)/Nb(50)/4H-SiC sample without applying the CF4:O2 etching process degraded just after 25-hour and lost ohmic behavior after 50-hour aging, the Ni(75)/Nb(25)/4H-SiC contact undergone CF4:O2 surface treatment still showed excellent stability after aging for 100 hours at 500℃. Though X-ray diffraction results indicated that the chemical compounds remained stable during the aging process, transmission electron microscopy showed that there was a redistribution of the chemical compounds at the interface of the contact after 500℃ aging. The depth distribution of the elements and energy dispersive X-ray analyses revealed that the contribution of carbon agglomeration at the interface accounted for the degradation of the sample without applying the etching process. Whereas the well-controlled excess carbon atoms of the contact undergone CF4:O2 treatment ensured the stability of this contact when operating at high-temperature ambient.

The Method of Low-Temperature ICP Etching of InP/InGaAsP Heterostructures in Cl2-Based Plasma for Integrated Optics Applications

Chlorine processes are widely used for the formation of waveguide structures in InP-based optoelectronics. Traditionally, ICP etching of InP in a Cl2-based plasma requires substrate temperatures in the range of 150–200 °C. This condition is mandatory, since during the etching process low-volatility InClx components are formed and at insufficient temperatures are deposited onto substrate, leading to the formation of defects and further impossibility of the formation of waveguide structures. The need to preheat the substrate limits the application of chlorine processes. This paper presents a method of ICP etching an InP/InGaAsP heterostructure in a Cl2/Ar/N2 gas mixture. A feature of the developed method is the cyclic etching of the heterostructure without preliminary heating. The etching process starts at room temperature. In the optimal etching mode, the angle of inclination of the sidewalls of the waveguides reached 88.8° at an etching depth of more than 4.5 μm. At the same time, the surface roughness did not exceed 30 nm. The selectivity of the etching process with respect to the SiNx mask was equal to 9. Using the developed etching method, test integrated waveguide elements were fabricated. The fabricated active integrated waveguide (p-InP epitaxial layers were not removed) with a width of 2 μm demonstrated an optical loss around 11 ± 1.5 dB/cm at 1550 nm. The insertion loss of the developed Y- and MMI-splitters did not exceed 0.8 dB.

Fabrication of (ZnO)x: (Cu)1-x/PSi Solar Cell Using Laser Induced Plasma Technique

Fabrication of PSi is generated successfully depending upon photo-electrochemical etching process. The purpose is to differentiate the characterization of the PSi monolayer based on c-silicon solar cell compared to the bulk silicon alone. The surface of ordinary p-n solar cell has been reconstructed on the n-type region of (100) orientation with resistivity (3.2.cm) in hydrofluoric (HF) acid at a concentration of 2 ml was used to in order to enhance the conversion efficiency with 10-minute etching time and current density of 50 mA/cm2, The morphological properties (AFM) as well as the electrical properties have been investigated (J-V). The atomic force microscopy investigation reveals a rugged silicon surface with porous structure nucleating during the etching process (etching time), resulting in an expansion in depth and an average diameter of (40.1 nm). As a result, the surface roughness increases. The electrical properties of prepared PS, namely current density-voltage characteristics in the dark, reveal that porous silicon has a sponge-like structure and that the pore diameter increases with increasing etching current density and the number of shots increasing this led that the solar cell efficiency was in the range of (1-2%), resulting in improved solar cell performance.

Optimization of deep silicon etching process for microstructures fabrication

The paper presents the study of cyclic process of deep anisotropic silicon etching, called Oxi-Etch, in which the steps of etching and oxidation alternate, allowing deep etching of silicon with an anisotropic profile. This process forms typical for cyclic etching process sidewall profile called scalloping. Opportunities for modification and optimization of the process for specific application were investigated. The effects of optimization of the bias voltage and the duration of the etching step on the parameters of the resulting structures, such as the etching depth, wall roughness, and the accuracy of transferring the lithographic size, are considered. Balance between etch rate and scalloping was established.

Effect of Machining Limiting Factors on Drilling Progress during Spark Assisted Chemical Engraving (SACE): General Trends

Spark Assisted Chemical Engraving (SACE) is a micro-machining technology for non-conductive materials, mainly glass, based on thermal assisted etching. Generally, during SACE, drilling proceeds at a fast rate reaching 100 µm/s for the first 100 µm and then it slows down for depths higher than 300 µm. While several techniques have been proposed to establish faster drilling, they mainly rely on tuning the machining parameters to enhance the machining performance. However, with this approach machining parameters need to be constantly tuned to achieve certain machining performance depending on the size of the tool and the features needed. Therefore, this necessitates further work to enhance understanding regarding the SACE machining process fundamentals in order to enhance machining speed and quality. Since SACE is a thermal assisted etching process, both local heating and flushing of electrolyte in the machining zone are required. However, to the authors’ knowledge there is not any study that attempts to analyze the effect of each of these machining limiting factors on the machining performance. This work attempts to clarify the effect of each flushing and heating on the drilling progress for hole depths higher than 100 microns. It therefore provides a deeper understanding of the fundamentals of the SACE machining process.

Research on Trench Etching and Photolithography Process of SiC Trench MOSFET

In this paper, the development of trench etching process and photolithography process for 6-inch 4H-SiC trench-type power MOSFET devices is mainly studied. Among them, the etching process successfully solved the anisotropy of dry etching of SiC, the different etching rates of different crystal planes, the difficulty of controlling the angle of the trench sidewall, and the easy formation of micro-trenches at the corners, etc. Successfully realized trenches with etch depth greater than 1.2um and sidewall angle greater than 90° in SiC. Subsequently, the trench was filled with SiO2 to achieve no holes in the trench after filling, and then the photolithography process was studied. Photolithography process is resolved at the trench coating, exposing and developing the non-uniformity problem, achieve a full and uniform coating, self-aligned trench overlay and the overlay accuracy of less than 0.1um, and there is no residue of photoresist in the groove after development. This article uses scanning electron microscope (SEM) to measure the morphology of the trench after etching and photolithography to characterize the experimental results, and the results meet the process requirements. The successful development of this process will facilitate the research and development of deeper trench-type power MOSFET devices.