HF-QSRAM: Half-Select Free Quaternary SRAM Design with Required Peripheral Circuits for IoT/IoVT Applications

By using CNFET technology in 3a 2 nm node using a proposed SQI gate, two split bit-lines QSRAM architectures have been suggested to address the issue of increasing demand for storage capacity in IoT/IoVT applications. Peripheral circuits such as a novel quaternary to binary decoder for QSRAM have been offered. Various simulations on temperature, supply voltage, and access frequency have been done to evaluate and ensure the performance of the proposed SQI gate, suggested cells, and quaternary to binary decoder. Moreover, 1000 Monte-Carlo analyses on the fabrication parameters have been done to classify read and write delay and standby power of proposed cells along with PDP of proposed quaternary to binary decoder. It is worth mentioning that the PDP of the proposed SQI gate, decoder, and average power consumption of suggested HF-QSRAM cell reached 0.92 aJ, 4.13 aJ, and 0.15 µW, respectively, which are approximately 80%, 91%, and 33% improvements in comparison with the best existing designs in the literature.

Quantum Tunnelling based Ultra-compact and Energy Efficient Spiking Neuron enables Hardware Liquid State Machine

Low-power and low-area neurons are essential for hardware implementation of large-scale SNNs. Various novel physics based leaky-integrate-and-fire (LIF) neuron architectures have been proposed with low power and area, but are not compatible with CMOS technology to enable brain scale implementation of SNN. In this paper, for the first time, we demonstrate hardware implementation of LSM reservoir using band-to-band-tunnelling (BTBT) based neuron. A low-power thresholding circuit and current-to-voltage converter design are proposed. We further propose a predistortion technique to linearize a nonlinear neuron without any area and power overhead. We establish the equivalence of the proposed neuron with the ideal LIF neuron to demonstrate its versatility. To verify the effect of the proposed neuron, a 36-neuron LSM reservoir is fabricated in GF-45nm PDSOI technology. We achieved 5000x lower energy-per-spike at a similar area, 50x less area at a similar energy-per-spike, and 10x lower standby power at a similar area and energy-per-spike. Such overall performance improvement enables brain scale computing.

On High-Temperature Galvanic Elements of Stand­by Power Supply Sources based on Energy Condensed Systems

Study of ignition, combustion and electrochemical processes occurring in thin multilayer high-temperature galvanic elements derived from low-gas energy condensed systems was carried out. The research results made it possible to design a wide range of multifunctional standby power supply sources with improved performance, differing in application types, initiation modes, activation and operation times, overall dimensions and shape.

Stability of a Fe-Rich Cathode Catalyst in an Anion Exchange Membrane Fuel Cell

Fe-rich alloys have been widely studied as catalyst materials for the cathodic oxygen reduction reaction (ORR) in hydrogen fuel cells, and many have shown high activities. The stability of Fe-rich catalysts has also been researched, and some studies have shown promising results using an accelerated stress test (AST), which uses a potential cycling method. However, for commercial fuel cell applications, such as standby power systems, the catalyst has to tolerate a high potential for a long period, which can not be represented by the AST test. In this paper, the cathode stability of a Fe-rich catalyst was studied using a standby cell potential of 0.9V, a potential shown to be challenging for the competing Pt catalysts. After 1500 hrs of testing, significant morphology changes of both the tested cathode and anode were found due to a Fe leaching process. Other alloy materials, including Ni, Cr, and Mn, were also found leached out along with the Fe species from the catalyst framework. The results are a cautionary note for using Fe based catalysts for AEMFC cathodes.

Reduction of Reactive Power Waste of Inductive Electrical Appliances using Power Factor Correction

Electricity is the primary source of power in most countries including Sri Lanka, and saving or minimising the waste of it has become crucial in facing the world power crisis. Electrical power is wasted in various ways including reactive power waste due to induction and capacitance of appliances, and standby power loss. These two contribute most to the waste. This paper focuses on reducing the reactive power waste of inductive electrical appliances commonly used in home and office by increasing the power factor. An attempt was made to reduce the power waste of inductive electrical appliances by connecting a capacitor bank with a variable capacitance in parallel with the appliance. Optimal capacitance and the power factor are determined using the capacitor bank. Results indicate about 30 percent of power saving could be achieved for fluorescent tube lamps using a power factor correction. A maximum power factor of 0.93 is achieved at the capacitance value of 2.99 F. It is not possible, by this method, to increase the power factor of more capacitive equipment such as CFL bulbs and ceiling fans. In this case, power minimisation could be tried connecting inductors in parallel with the equipment. Power factor and power consumption of home electrical appliances were measured for advising the general public of high power consuming equipment, especially in stand-by mode. To attain a further reduction of power waste it is proposed to measure inductance, capacitance and resistance of appliances using Hendry, Farad and Ohm meter. Total impedance can then be calculated and the power waste could be minimised using appropriate capacitors and/or inductors. Keywords: reactive power, power factor, power waste, reactive power waste, power minimisation

Power Management in Low-Power MCUs for Energy IoT Applications

In this paper, we identify and address the problems of designing effective power management schemes in low-power MCU design. Firstly, this paper proposes an application-based multipower domain architecture along with a variety of working modes to effectively realize the hierarchical control of power consumption. Furthermore, devices in energy IoT (eIoT) do not always work under the main power supply. When the main power supply is unavailable, the standby power supply (usually the battery) needs to maintain the operation and save the data. In order to ensure the complete isolation between these two power sources, it is always necessary to insert a diode in both select-conduction paths, respectively. In this paper, we built a stable and smooth power switching circuit into the chip, which can effectively avoid the diode voltage loss and reduce the BoM cost. In addition, in the sleep mode, considering the relaxed output voltage range and a limited driving capability requirement, an ultra-low-power standby power circuit is proposed, which can autonomously replace the internal LDO when in sleep, further reducing the sleep power consumption under the main power supply. Fabricated in a standard 0.11 μm CMOS process, our comparative analysis demonstrates substantial reduction in power consumption from 1 μA to 0.1 μA.