The high power consumption during circuit test process can produce unwanted failures or take effects on circuit
reliability, therefore the reduction of both peak power and average power of circuit test is necessary. A test pattern generation
approach is presented in this paper for the delay faults in digital circuits, the approach makes use of the evolution
method with the hybrid strategies to produce the test vectors with low power consumption. First of all, a pair of vectors
that may detect a delay fault is coded as an individual. A lot of individuals constitute the populations. Secondly, the test
vectors with low power are produced by the evolution of these populations. Many new individuals are randomly produced
and are added into every evolution step, and the mutation mode of individuals is related to other individuals in the
current population. A lot of experimental results show that the test vectors with low power for the delay faults in digital
circuits can be produced by the approach proposed in this paper, and the approach can get the large reduction of power
consumption when compared with random test generation algorithm.
Test Pattern Generation with Low Power for Delay Faults in Digital Circuits by Evolution Method with Hybrid Strategies
