scholarly journals Silicon nanoparticle charge trapping memory cell

2014 ◽  
Vol 8 (7) ◽  
pp. 629-633 ◽  
Author(s):  
Nazek El-Atab ◽  
Ayse Ozcan ◽  
Sabri Alkis ◽  
Ali K. Okyay ◽  
Ammar Nayfeh
2006 ◽  
Vol 933 ◽  
Author(s):  
Chang-Hyun Lee ◽  
Changseok Kang ◽  
Yoocheol Shin ◽  
Jaesung Sim ◽  
Jongsun Sel ◽  
...  

ABSTRACTWe present the TANOS (Si-Oxide-SiN-Al2O3-TaN) cell with 40 Å-thick tunnel oxide erased by Fowler-Nordheim (FN) tunneling of hole. Thanks to introducing high-k dielectrics, alumina (Al2O3) as a blocking oxide, the erase threshold voltage can be maintained to less than - 3.0 V, meaning hole-trapping in SiN. We extracted the nitride trap densities of electron and hole for the TANOS cell. It is demonstrated that the TANOS structure is very available to investigate the trap density with shallower energy. The energy level of hole trap (1.28 eV) is found to be deeper than that of electron (0.8 eV). As the cycling stress is performed, persistent hole-trapping is observed unlike endurance characteristics of conventional floating-gate cell. The hole trapping during the cycling stress can be attributed to two possibilities. The injected holes are trapped in neutral trap of tunnel oxide and residue of holes which is not somewhat compensated by injected electrons may be accumulated in SiN. It is demonstrated the erase operation of the TANOS cell is governed by Fowler-Nordheim tunneling of hole due to the field concentration across the tunnel oxide.


AIP Advances ◽  
2013 ◽  
Vol 3 (11) ◽  
pp. 112116 ◽  
Author(s):  
Nazek El-Atab ◽  
Ayman Rizk ◽  
Ali K. Okyay ◽  
Ammar Nayfeh

2018 ◽  
Vol 35 (11) ◽  
pp. 118501 ◽  
Author(s):  
Yan-Nan Xu ◽  
Jin-Shun Bi ◽  
Gao-Bo Xu ◽  
Bo Li ◽  
Kai Xi ◽  
...  

2012 ◽  
Vol 33 (12) ◽  
pp. 1714-1716 ◽  
Author(s):  
Feyza B. Oruc ◽  
Furkan Cimen ◽  
Ayman Rizk ◽  
Mohammad Ghaffari ◽  
Ammar Nayfeh ◽  
...  

2008 ◽  
Vol 17 (7) ◽  
pp. 2678-2682 ◽  
Author(s):  
Song Yun-Cheng ◽  
Liu Xiao-Yan ◽  
Du Gang ◽  
Kang Jin-Feng ◽  
Han Ru-Qi

2007 ◽  
Vol 997 ◽  
Author(s):  
Torsten Mueller ◽  
C. Kleint ◽  
C. Fitz ◽  
M. Isler ◽  
S. Riedel ◽  
...  

AbstractA 63nm Twin Flash memory cell with a size of 0.0225μm2 per 2 (or 4) bits is presented. To achieve small cell areas, a buried bit line and an aggressive gate length of 100 nm are the key features of this cell together with a minimum thermal budget processing. A novel epitaxial CoSi2 process allows the salicidation of local buried bitlines with only a few tens of nanometer width.


2006 ◽  
Vol 45 (4B) ◽  
pp. 3179-3184
Author(s):  
Lei Sun ◽  
Liyang Pan ◽  
Huiqing Pang ◽  
Ying Zeng ◽  
Zhaojian Zhang ◽  
...  

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