loop body

Author(s):  
Martin H. Weik
Keyword(s):  
1997 ◽  
Vol 07 (04) ◽  
pp. 379-392 ◽  
Author(s):  
Alain Darte ◽  
Georges-André Silber ◽  
Frédéric Vivien

Tiling is a technique used for exploiting medium-grain parallelism in nested loops. It relies on a first step that detects sets of permutable nested loops. All algorithms developed so far consider the statements of the loop body as a single block, in other words, they are not able to take advantage of the structure of dependences between different statements. In this paper, we overcame this limitation by showing how the structure of the reduced dependence graph can be taken into account for detecting more permutable loops. Our method combines graph retiming techniques and graph scheduling techniques. It can be viewed as an extension of Wolf and Lam's algorithm to the case of loops with multiple statements. Loan independent dependences play a particular role in our study, and we show how the way we handle them can be useful for fine-grain loop parallelization as well.


2021 ◽  
Vol 5 (OOPSLA) ◽  
pp. 1-29
Author(s):  
Kasra Ferdowsifard ◽  
Shraddha Barke ◽  
Hila Peleg ◽  
Sorin Lerner ◽  
Nadia Polikarpova

One vision for program synthesis, and specifically for programming by example (PBE), is an interactive programmer's assistant, integrated into the development environment. To make program synthesis practical for interactive use, prior work on Small-Step Live PBE has proposed to limit the scope of synthesis to small code snippets, and enable the users to provide local specifications for those snippets. This paradigm, however, does not work well in the presence of loops. We present LooPy, a synthesizer integrated into a live programming environment, which extends Small-Step Live PBE to work inside loops and scales it up to synthesize larger code snippets, while remaining fast enough for interactive use. To allow users to effectively provide examples at various loop iterations, even when the loop body is incomplete, LooPy makes use of live execution , a technique that leverages the programmer as an oracle to step over incomplete parts of the loop. To enable synthesis of loop bodies at interactive speeds, LooPy introduces Intermediate State Graph , a new data structure, which compactly represents a large space of code snippets composed of multiple assignment statements and conditionals. We evaluate LooPy empirically using benchmarks from competitive programming and previous synthesizers, and show that it can solve a wide variety of synthesis tasks at interactive speeds. We also perform a small qualitative user study which shows that LooPy's block-level specifications are easy for programmers to provide.


Mathematics ◽  
2020 ◽  
Vol 8 (3) ◽  
pp. 317
Author(s):  
Taixia Cheng ◽  
Zhinan Wu ◽  
Xiaowu Li ◽  
Chan Wang

Point orthogonal projection onto a spatial algebraic curve plays an important role in computer graphics, computer-aided geometric design, etc. We propose an algorithm for point orthogonal projection onto a spatial algebraic curve based on Newton’s steepest gradient descent method and geometric correction method. The purpose of Algorithm 1 in the first step of Algorithm 4 is to let the initial iteration point fall on the spatial algebraic curve completely and successfully. On the basis of ensuring that the iteration point fallen on the spatial algebraic curve, the purpose of the intermediate for loop body including Step 2 and Step 3 is to let the iteration point gradually approach the orthogonal projection point (the closest point) such that the distance between them is very small. Algorithm 3 in the fourth step plays an important double acceleration and orthogonalization role. Numerical example shows that our algorithm is very robust and efficient which it achieves the expected and ideal result.


Author(s):  
Pierre-Loïc Garoche

This chapter focuses on floating-point semantics. It first outlines these semantics. The chapter then revisits previous results and adapts them to account for floating-point computations, assuming a bound on the rounding error is provided. A last part focuses on the approaches to bound these imprecisions, over-approximating the floating-point errors. Here, provided bounds on each variable, computing the floating-point error can be performed with classical interval-based analysis. Kleene-based iterations with interval abstract domain provide the appropriate framework to compute such bounds. This is even simpler in this setting because of the focus on bounding the floating-point error on a single call of the dynamic system transition function, that is, a single loop body execution without internal loops.


Author(s):  
Nguyen Ngoc Khai ◽  
Truong Anh Hoang ◽  
Dang Duc Hanh

Estimating memory required by complex programs is a well-known research topic. In this work, we build a type system to statically estimate the memory bounds required by shared variables in software transactional memory (STM) programs. This work extends our previous works with additional language features such as explicitly declared shared variables, introduction of primitive types, and allowing loop body to contain any statement, not required to be well-typed as in our previous works. Also, the new type system has better compositionality compared to available type systems.


2011 ◽  
Vol 317-319 ◽  
pp. 146-149
Author(s):  
Hui Yang ◽  
Shu Ming Chen ◽  
Tie Bin Wu

Instruction compression technique overcomes the drawbacks of traditional VLIW architectures with low density in the instruction cache. However, the separated long instruction word was arranged into two cache line. It comes to be a bottleneck problem for VLIW architecture processor performance because these split long instruction word can not be fetched and issued simultaneously. A novel two-level instruction issue window mechanism is proposed in this paper. It solves the instruction fetch and issue problem in separating instruction words. It provides more effective and continuous instruction flow, and stores one iteration of the loop body to support software pipeline technique, which improves VLIW DSP processor performance effectively. Proposed machanism was synthesized to evaluate its overall costs, and the performance speedup result for DSP/IMG library bencharks using the cycle accurate simulator are presented.


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