Compiler-Directed Dynamic Frequency and Voltage Scheduling

Author(s):  
Chung-Hsing Hsu ◽  
Ulrich Kremer ◽  
Michael Hsiao
Keyword(s):  
2021 ◽  
pp. 136943322110262
Author(s):  
Mohammad H Makiabadi ◽  
Mahmoud R Maheri

An enhanced symbiotic organisms search (ESOS) algorithm is developed and presented. Modifications to the basic symbiotic organisms search algorithm are carried out in all three phases of the algorithm with the aim of balancing the exploitation and exploration capabilities of the algorithm. To verify validity and capability of the ESOS algorithm in solving general optimization problems, the CEC2014 set of 22 benchmark functions is first optimized and the results are compared with other metaheuristic algorithms. The ESOS algorithm is then used to optimize the sizing and shape of five benchmark trusses with multiple frequency constraints. The best (minimum) mass, mean mass, standard deviation of the mass, total number of function evaluations, and the values of frequency constraints are then compared with those of a number of other metaheuristic solutions available in the literature. It is shown that the proposed ESOS algorithm is generally more efficient in optimizing the shape and sizing of trusses with dynamic frequency constraints compared to other reported metaheuristic algorithms, including the basic symbiotic organisms search and its other recently proposed improved variants such as the improved symbiotic organisms search algorithm (ISOS) and modified symbiotic organisms search algorithm (MSOS).


2015 ◽  
Vol 23 (22) ◽  
pp. 29245 ◽  
Author(s):  
Qian Zhou ◽  
Jie Qin ◽  
Weilin Xie ◽  
Zhangweiyi Liu ◽  
Yitian Tong ◽  
...  

2006 ◽  
Vol 12 (4) ◽  
pp. 334-339 ◽  
Author(s):  
Mohammad M.N. Hamarsheh ◽  
Mohamad K. Abdullah ◽  
S. Khatun ◽  
Hossam M.H. Shalaby

2015 ◽  
Vol 25 (01) ◽  
pp. 1640005 ◽  
Author(s):  
Hitoshi Oi

Dynamic frequency scaling (DFS) is a feature commonly found in modern processors. It lowers the clock frequency of a core according to the load level and reduces the power consumption. In this paper, we present a case study of tuning DFS parameters on a platform with an AMD Phenom II X6 using the SPECjEnterprise2010 (jEnt10) and SPECjbb2005 (jbb05) as the workload. In jEnt10, a longer sampling period of core utilization (up to 1.5[Formula: see text]s) reduced the power by 6[Formula: see text]Watt at 25% load level. At 50% load level, combining it with an increased threshold level (98%) to switch the clock frequency further reduced the power consumption by up to 10[Formula: see text]Watt. In jbb05, stretching the sampling period was only effective up to 0.5[Formula: see text]s. The maximum reduction was observed at around 60% load level. Raising the threshold level was not effective for jbb05.


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