Ultra Low Voltage SRAM Design

2009 ◽  
pp. 89-126 ◽  
Author(s):  
Naveen Verma ◽  
Anantha P. Chandrakasan
Keyword(s):  
Low Voltage ◽  
Sram Design

Ultra-compact SRAM design using TFETs for low power low voltage applications

2016 ◽  
Author(s):  
Navneet Gupta ◽  
Adam Makosiej ◽  
Andrei Vladimirescu ◽  
Amara Amara ◽  
Costin Anghel
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Sram Design

A 256-kb 65-nm Sub-threshold SRAM Design for Ultra-Low-Voltage Operation

2007 ◽  
Vol 42 (3) ◽  
pp. 680-688 ◽  
Author(s):  
Benton Highsmith Calhoun ◽  
Anantha P. Chandrakasan
Keyword(s):  
Low Voltage ◽  
Low Voltage Operation ◽  
Sram Design

scholarly journals Performance comparison of SRAM cells in 45NM technology in the presence of a memory cell control circuit

2018 ◽  
Vol 7 (4.5) ◽  
pp. 645
Author(s):  
Sanket Jagadale ◽  
Aniket Phapale ◽  
T. V. Sai Varun Sasthry ◽  
V. S. Kanchana Bhaaskaran
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Memory Cell ◽  
Performance Comparison ◽  
Control Circuit ◽  
Stable Operation ◽  
Memory Retention ◽  
Cell Control ◽  
Noise Margin ◽  
Sram Design

Lowering power consumption and increasing the noise margin have become the two most important aspects to be considered in SRAM design. Additionally, a stable operation with good memory retention capability has gained greater importance in obtaining good yield at low-voltage and low-power SRAM designs, due to the fact that parameter variations play a major role in scaled technologies. In this paper, the 6T SRAM, 7T low power SRAM and 7T multi threshold low power SRAM designs are designed, to incorporate power gating technique. The architecture of each of the SRAM designs and their working are analyzed thoroughly. The outputs of the read, write and hold operations with transient response are observed and the power dissipation and static noise margin (SNM) of the each of the SRAM cells is calculated and compared. The paper also presents new power reduction solution through the cell control circuit which reduces the unwanted and spurious switching activities during read and writes operations. The paper demonstrates the reduction of the power con- sumption through the use of cell control circuit.   

Low voltage SRAM design using tunneling regime of CNTFET

2014 ◽  
Author(s):  
Zubair Ahmed ◽  
Khawar Sarfraz ◽  
Lining Zhang ◽  
Mansun Chan
Keyword(s):  
Low Voltage ◽  
Sram Design

scholarly journals Charge recycling 8T SRAM design for low voltage robust operation

2016 ◽  
Vol 70 (1) ◽  
pp. 25-32 ◽  
Author(s):  
Xu Wang ◽  
Chao Lu ◽  
Zhigang Mao
Keyword(s):  
Low Voltage ◽  
Sram Design ◽  
Charge Recycling

scholarly journals Design of Low Power Memory Architecture using 10t Sram Array

2019 ◽  
Vol 8 (4) ◽  
pp. 10650-10653
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
Low Voltage ◽  
Supply Voltage ◽  
Random Access ◽  
Total Power ◽  
Access Time ◽  
Stable Operation ◽  
Sram Cell ◽  
Sram Design

The main aim of electronics is to design low power devices due to the prevalent usage of powered gadget. Ultra low voltage operation of memory cells has become a subject of a lot of interest because of its applications in terribly low energy computing. The stable operation of static random access memory (SRAM) is important for the success of low voltage SRAM and it is achieved by parameter variations of scaled technologies. The power consumption and access time of the SRAM is also a complex parameter due to the unavoidable switching activities of the number of transistors used for different blocks like, SRAM cell, access transistors, pre-charge circuit, sense amplifier and decoders. It has been shown that conventional 6T SRAM fail to achieve low power and delay operation. The proposed 10T SRAM design gives an approach towards the hold power dissipation. The designed circuit has 10 transistors out of that 2 transistors are used as sleep transistor. The sleep transistors are used as switches. Such as header and footer switches and the switches are turned on during active mode of operations and turned off during idle or standby mode of operations. The designed SRAM cell also has conducting pMOS circuit, which can reduces the total power dissipation. The SRAM cell is simulated by using Cadence tool. A supply voltage of 1.8V is used which makes it enough for low power applications. The power obtained as 761.7mW, which reduces 15% of conventional 6T SRAM design. The delay obtained as 125.6ns, which reduces 45% of conventional 6T SRAM.

Sign in / Sign up

Export Citation Format

Share Document