scholarly journals Design of Low Power Memory Architecture using 10t Sram Array

2019 ◽  
Vol 8 (4) ◽  
pp. 10650-10653
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
Low Voltage ◽  
Supply Voltage ◽  
Random Access ◽  
Total Power ◽  
Access Time ◽  
Stable Operation ◽  
Sram Cell ◽  
Sram Design

The main aim of electronics is to design low power devices due to the prevalent usage of powered gadget. Ultra low voltage operation of memory cells has become a subject of a lot of interest because of its applications in terribly low energy computing. The stable operation of static random access memory (SRAM) is important for the success of low voltage SRAM and it is achieved by parameter variations of scaled technologies. The power consumption and access time of the SRAM is also a complex parameter due to the unavoidable switching activities of the number of transistors used for different blocks like, SRAM cell, access transistors, pre-charge circuit, sense amplifier and decoders. It has been shown that conventional 6T SRAM fail to achieve low power and delay operation. The proposed 10T SRAM design gives an approach towards the hold power dissipation. The designed circuit has 10 transistors out of that 2 transistors are used as sleep transistor. The sleep transistors are used as switches. Such as header and footer switches and the switches are turned on during active mode of operations and turned off during idle or standby mode of operations. The designed SRAM cell also has conducting pMOS circuit, which can reduces the total power dissipation. The SRAM cell is simulated by using Cadence tool. A supply voltage of 1.8V is used which makes it enough for low power applications. The power obtained as 761.7mW, which reduces 15% of conventional 6T SRAM design. The delay obtained as 125.6ns, which reduces 45% of conventional 6T SRAM.

scholarly journals Comparative analysis of SRAM cell with leakage power reduction approaches

2018 ◽  
Vol 7 (2.7) ◽  
pp. 863
Author(s):  
Damarla Paradhasaradhi ◽  
Kollu Jaya Lakshmi ◽  
Yadavalli Harika ◽  
Busa Ravi Teja Sai ◽  
Golla Jayanth Krishna
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
Low Voltage ◽  
Power Saving ◽  
Vital Role ◽  
Power Reduction ◽  
Leakage Power ◽  
Access Time ◽  
Chip Area ◽  
Sram Cell

In deep sub-micron technologies, high number of transistors is mounted onto a small chip area where, SRAM plays a vital role and is considered as a major part in many VLSI ICs because of its large density of storage and very less access time. Due to the demand of low power applications the design of low power and low voltage memory is a demanding task. In these memories majority of power dissipation depends on leakage power. This paper analyzes the basic 6T SRAM cell operation. Here two different leakage power reduction approaches are introduced to apply for basic 6T SRAM. The performance analysis of basic SRAM cell, SRAM cell using drowsy-cache approach and SRAM cell using clamping diode are designed at 130nm using Mentor Graphics IC Studio tool. The proposed SRAM cell using clamping diode proves to be a better power reduction technique in terms of power as compared with others SRAM structures. At 3.3V, power saving by the proposed SRAM cell is 20% less than associated to basic 6T SRAM Cell.

scholarly journals A Low Leakage 9T SRAM Cell With Improve Stability in Sub-Threshold Region for IoT Applications

2021 ◽  
Author(s):  
Harekrishna Kumar ◽  
V.K Tomar
Keyword(s):  
Power Dissipation ◽  
Supply Voltage ◽  
Random Access ◽  
Mean Value ◽  
Access Time ◽  
Threshold Region ◽  
Low Leakage ◽  
Noise Margin ◽  
Sram Cell ◽  
Forward Body Bias

Abstract This paper presents a single-ended read and differential write half select free 9T static random access memory (SRAM) cell operates in the sub-threshold region. Proposed 9T SRAM cell shows a reasonable reduction in read and write power dissipation by a factor of 1.41× and 2.1× respectively as of conventional 6T (Conv.6T) SRAM cell. The stacking of transistors at core latch network minimizes the leakage power of the cell. The read static noise margin (RSNM) and write margin (WM) are upgraded by 2.16× and 2.06× respectively as of Conv.6T cell. A forward body bias technique is utilized in read path which results to decreases in read access time by a factor of 2.72× as of standard 6T SRAM cell. The mean value of Ion/Ioff ratio of the proposed cell is improved by 2.92× as compared to the Conv.6T SRAM cell. It is attributed to a reduction in bit-line leakage current. To achieve more soundness in characteristics of the proposed 9T SRAM cell, process variation effect on RSNM, power dissipation, and read current is calculated through Monte Carlo (MC) simulation at 5000 points. The obtained results are compared with reference SRAM cells at 0.3V supply voltage.

Analysis of 6T SRAM Cell in Different Technologies

2017 ◽  
Vol MCSP2017 (01) ◽  
pp. 7-10 ◽  
Author(s):  
Subhashree Rath ◽  
Siba Kumar Panda
Keyword(s):  
Low Power ◽  
Data Storage ◽  
Low Voltage ◽  
Random Access ◽  
Storage Device ◽  
Cmos Process ◽  
Process Technology ◽  
Digital Devices ◽  
Noise Margin ◽  
Sram Cell

Static random access memory (SRAM) is an important component of embedded cache memory of handheld digital devices. SRAM has become major data storage device due to its large storage density and less time to access. Exponential growth of low power digital devices has raised the demand of low voltage low power SRAM. This paper presents design and implementation of 6T SRAM cell in 180 nm, 90 nm and 45 nm standard CMOS process technology. The simulation has been done in Cadence Virtuoso environment. The performance analysis of SRAM cell has been evaluated in terms of delay, power and static noise margin (SNM).

scholarly journals Comprehensive Analysis of SRAM Cell Architectures With 18nm FinFET for Low Power Applications

2021 ◽  
Author(s):  
T. Santosh Kumar ◽  
Suman Lata Tripathi
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Power Dissipation ◽  
Supply Voltage ◽  
Reduction Technique ◽  
Leakage Currents ◽  
Leakage Reduction ◽  
Sram Cell ◽  
Supply Voltage Scaling ◽  
Better Than

Abstract The SRAM cells are used in many applications where power consumption will be the main constraint. The Conventional 6T SRAM cell has reduced stability and more power consumption when technology is scaled resulting in supply voltage scaling, so other alternative SRAM cells from 7T to 12T have been proposed which can address these problems. Here a low power 7T SRAM cell is suggested which has low power consumption and condensed leakage currents and power dissipation. The projected design has a leakage power of 5.31nW and leakage current of 7.58nA which is 84.9% less than the 7T SRAM cell without using the proposed leakage reduction technique and it is 22.4% better than 6T SRAM and 22.1% better than 8T SRAM cell when both use the same leakage reduction technique. The cell area of the 7T SRAM cell is 1.25µM2, 6T SRAM is 1.079µM2 and that of 8T SRAM is 1.28µM2all the results are simulated in cadence virtuoso using 18nm technology.

Design of a Bit-Interleaved Low Power 10T SRAM Cell with Enhanced Stability

2020 ◽  
pp. 2150142
Author(s):  
R. Manoj Kumar ◽  
P. V. Sridevi
Keyword(s):  
Low Power ◽  
Supply Voltage ◽  
Random Access ◽  
Leakage Power ◽  
High Threshold ◽  
Point Selection ◽  
Cross Point ◽  
Design Metrics ◽  
Fully Differential ◽  
Sram Cell

The technology is shrinking in recent days which leads to growing concerns related to various design metrics. Leakage power tends to grow with the array size as most of the Static Random Access Memory (SRAM) cells operate in standby mode. The data to be written into the SRAM become difficult as the supply voltage decreases. So, stability in write mode requires enhancement. As SRAM is used for the on-chip computations, the faster write operation is required. The half-select issue in SRAM design needs to be eliminated so that bit interleaving architecture can be employed for the SRAM array enabling the protection from soft errors. A new Proposed 10 Transistor Bit-Interleaved SRAM cell has been designed addressing the above concerns. Employment of high-threshold voltage devices in read path and absence of NMOS device in one of the inverters reduces leakage power. Cut-off switch enables faster write operation and enhanced write stability. Cross point selection in write mode eliminates the half-select issue observed by carrying 1000 Monte-Carlo simulations. It has lower leakage power while holding 0 compared to 8 Transistor, Fully Differential 8 Transistor and Write Assist Low Power 11 Transistor SRAM cells at the worst fast-fast process corner for 0.9 V supply voltage. Write 1 Power Delay Product is lower than 8 Transistor, Fully Differential 8 Transistor and Write Assist Low Power 11 Transistor SRAM cells at slow-slow corner at 0.9V supply voltage. All the design metrics have been evaluated by performing post-layout simulation in Cadence Virtuoso in 45-nm technology.

High-Swing, High-Resolution, Low-Power, Low-Area Voltage-Mode LTA/WTA Circuits

2015 ◽  
Vol 24 (07) ◽  
pp. 1550103 ◽  
Author(s):  
Mohammad Soleimani ◽  
Siroos Toofan ◽  
Mostafa Yargholi
Keyword(s):  
High Resolution ◽  
Low Power ◽  
Power Dissipation ◽  
Supply Voltage ◽  
Rank Order ◽  
Active Area ◽  
Total Power ◽  
Common Source ◽  
Cmos Process ◽  
Process Technology

In this paper, a general architecture for analog implementation of loser/winner-take-all (LTA/WTA) and other rank order circuits is presented. This architecture is composed of a differential amplifier with merged n-inputs and a merged common-source with active load (MCSAL) circuit to choose the desired input. The advantages of the proposed structure are simplicity, very high resolution, very low supply voltage requirements, very low output resistor, low power dissipation, low active area and simple expansion for multiple inputs by adding only three transistors for each extra input. The post-layout simulation results of proposed circuits are presented by HSPICE software in 0.35-μm CMOS process technology. The total power dissipation of proposed circuits is about 110-μW. Also, the total active area is about 550-μm2 for five-input proposed circuits, and would be negligibly increased for each extra input.

A 3.1 GB/s, 8 Kb, ZERO PRECHARGE, PIPELINED, HIGHLY STABLE 2-PORT 8T SRAM DESIGN IN 65 nm

2013 ◽  
Vol 22 (08) ◽  
pp. 1350069 ◽  
Author(s):  
ABHIJIT SIL ◽  
KRISHNA PRASAD BALUSU ◽  
CHANDRA SEKHAR GURRAM ◽  
MAGDY BAYOUMI
Keyword(s):  
High Speed ◽  
Data Transfer ◽  
Supply Voltage ◽  
Access Time ◽  
Pipeline Architecture ◽  
Noise Margin ◽  
Sram Cell ◽  
Sram Design ◽  
Cell Current ◽  
Stability Issues

As the supply voltage is reducing with feature size, SRAM cell design is going through severe stability issues. The issue becomes worse due to increased variability in below sub-100 nm technology. In this paper, we present a highly stable 2-port 8T SRAM cell for high speed application in 65 nm technology. The proposed design provides high stability under simultaneous read/write disturbed access without reducing the I cell . The cell characteristic is extensively examined under random variation. The dynamic read noise margin is improved by 95% over conventional dual port SRAM. The zero-precharge sensing and virtual ground scheme reduce read path leakage current by 95% over conventional high precharge 2-port SRAM cell. The cell current is improved by 52% over conventional design. Finally, an 8 Kb bit-interleaved 2-stage pipelined SRAM architecture is presented using proposed cell. The 2-stage pipeline architecture provides data transfer bandwidth of 3.1 GB/s. Area-efficient 2-stage decoder layout helps to avoid pseudo read problem in unselected cells without sacrificing memory access time.

scholarly journals TIQ Flash ADC Design using a Low Power Multiplier Based Encoder

2019 ◽  
Vol 8 (2S2) ◽  
pp. 226-229
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
Low Voltage ◽  
Supply Voltage ◽  
Power Supply Voltage ◽  
Large Power ◽  
Flash Adc ◽  
Analog To Digital ◽  
Tiq Comparator ◽  
The Impact

Threshold Inverter Quantization (TIQ) for applications of system-on-chip (SoC) depending on CMOS flash analog-to-digital converter (ADC). The TIQ technique which uses two cascaded CMOS inverters as a voltage comparator. However, this TIQ method must be created to meet the latest SoC trends, which force ADCs to be integrated with another electronic circuit on the chip and focus on low-power and low-voltage applications. TIQ comparator reduced the impact of variations in the process, temperature, and power supply voltage. Therefore, we obtained a higher TIQ flash ADC speed and resolution. TIQ flash ADC reduced / managed power dissipation. We obtain large power savings by managing the power dissipation in the comparator. Furthermore, the new comparator has a huge benefit in power dissipation and noise rejection comparative to the TIQ comparator [1]. The findings indicate that the TIQ flash ADC based on Modied mux attain heavy-speed transformation and has a tiny size, low-power dissipation and operation of lowvoltage compared to another flash ADCs.

scholarly journals Performance comparison of SRAM cells in 45NM technology in the presence of a memory cell control circuit

2018 ◽  
Vol 7 (4.5) ◽  
pp. 645
Author(s):  
Sanket Jagadale ◽  
Aniket Phapale ◽  
T. V. Sai Varun Sasthry ◽  
V. S. Kanchana Bhaaskaran
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Memory Cell ◽  
Performance Comparison ◽  
Control Circuit ◽  
Stable Operation ◽  
Memory Retention ◽  
Cell Control ◽  
Noise Margin ◽  
Sram Design

Lowering power consumption and increasing the noise margin have become the two most important aspects to be considered in SRAM design. Additionally, a stable operation with good memory retention capability has gained greater importance in obtaining good yield at low-voltage and low-power SRAM designs, due to the fact that parameter variations play a major role in scaled technologies. In this paper, the 6T SRAM, 7T low power SRAM and 7T multi threshold low power SRAM designs are designed, to incorporate power gating technique. The architecture of each of the SRAM designs and their working are analyzed thoroughly. The outputs of the read, write and hold operations with transient response are observed and the power dissipation and static noise margin (SNM) of the each of the SRAM cells is calculated and compared. The paper also presents new power reduction solution through the cell control circuit which reduces the unwanted and spurious switching activities during read and writes operations. The paper demonstrates the reduction of the power con- sumption through the use of cell control circuit.   

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