A Synchronization Mechanism for Multimedia Presentation

1996 ◽  
pp. 157-162
Author(s):  
Ying Cai ◽  
Grammati E. Pantziou
Keyword(s):  
Multimedia Presentation ◽  
Synchronization Mechanism

The prepracticum program in counselor training: A multimedia presentation

1972 ◽  
Author(s):  
Daniel W. Fullmer ◽  
Tim Gust ◽  
Jerrold Lee Shapiro ◽  
Tom Loomis ◽  
Paul J. Marano
Keyword(s):  
Counselor Training ◽  
Multimedia Presentation

MULTIMEDIA PRESENTATION OF SOLUTION OF LOGICAL MATH PROBLEMS AT PRIMARY SCHOOL

2016 ◽  
Vol 7 (1) ◽  
pp. 240-243
Author(s):  
Desislava Valcheva ◽  
◽  
Rumyana Papancheva ◽  
Keyword(s):  
Primary School ◽  
Multimedia Presentation ◽  
Math Problems

ОСОБЕННОСТИ АРХИТЕКТУРЫ И ОСНОВНЫЕ ХАРАКТЕРИСТИКИ АППАРАТНОГО ВИДЕОКОДЕКА СТАНДАРТА H.264 В СОСТАВЕ МИКРОСХЕМЫ 1892ВМ14Я

2020 ◽  
Vol 96 (3s) ◽  
pp. 89-96
Author(s):  
А.А. Беляев ◽  
Я.Я. Петричкович ◽  
Т.В. Солохина ◽  
И.А. Беляев
Keyword(s):  
Data Flow ◽  
System On Chip ◽  
Video Codec ◽  
Experimental Results ◽  
Video Sequences ◽  
Ip Core ◽  
Performance Measurements ◽  
Synchronization Mechanism ◽  
Architectural Features ◽  
On Chip

Рассмотрены особенности архитектуры и основные характеристики аппаратного видеокодека по стандарту H.264, входящего в состав микросхемы 1892ВМ14Я (MCom-02). Описан механизм синхронизации потоков данных на основе набора флагов событий. Приведены экспериментальные результаты измерения характеристик производительности разработанного видеокодека на реальных видеосюжетах при различных форматах передаваемого изображения. The paper considers main architectural features and characteristics of H.264 hardware video codec IP-core as a part of MCom- 02 system-on-chip (SoC). Bedides, it presents data flow synchronization mechanism based on event flags set, as well as experimental results of performance measurements for the designed video codec IP-core obtained for different video sequences and different image formats.

scholarly journals Enabling Parallelized-QEMU for Hardware/Software Co-Simulation Virtual Platforms

Electronics ◽  
2021 ◽  
Vol 10 (6) ◽  
pp. 759
Author(s):  
Edel Díaz ◽  
Raúl Mateos ◽  
Emilio J. Bueno ◽  
Rubén Nieto
Keyword(s):  
Performance Analysis ◽  
Industrial Application ◽  
The Novel ◽  
San Jose ◽  
Synchronization Mechanism ◽  
Grid Monitoring ◽  
Parallel Mode ◽  
Software And Hardware ◽  
Software Emulator ◽  
Dual Core

Presently, the trend is to increase the number of cores per chip. This growth is appreciated in Multi-Processor System-On-Chips (MPSoC), composed of more cores in heterogeneous and homogeneous architectures in recent years. Thus, the difficulty of verification of this type of system has been great. The hardware/software co-simulation Virtual Platforms (VP) are presented as a perfect solution to address this complexity, allowing verification by simulation/emulation of software and hardware in the same environment. Some works parallelized the software emulator to reduce the verification times. An example of this parallelization is the QEMU (Quick EMUlator) tool. However, there is no solution to synchronize QEMU with the hardware simulator in this new parallel mode. This work analyzes the current software emulators and presents a new method to allow an external synchronization of QEMU in its parallelized mode. Timing details of the cores are taken into account. In addition, performance analysis of the software emulator with the new synchronization mechanism is presented, using: (1) a boot Linux for MPSoC Zynq-7000 (dual-core ARM Cortex-A9) (Xilinx, San Jose, CA, USA); (2) an FPGA-Linux co-simulation of a power grid monitoring system that is subsequently implemented in an industrial application. The results show that the novel synchronization mechanism does not add any appreciable computational load and enables parallelized-QEMU in hardware/software co-simulation virtual platforms.

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