scholarly journals CLort: High Throughput and Low Energy Network Intrusion Detection on IoT Devices with Embedded GPUs

2018 ◽  
pp. 187-202 ◽  
Author(s):  
Charalampos Stylianopoulos ◽  
Linus Johansson ◽  
Oskar Olsson ◽  
Magnus Almgren
Keyword(s):  
Intrusion Detection ◽  
High Throughput ◽  
Low Energy ◽  
Network Intrusion Detection ◽  
Network Intrusion ◽  
Iot Devices ◽  
Energy Network

High throughput and low area cost FPGA‐based signature match circuit for network intrusion detection

2009 ◽  
Vol 32 (3) ◽  
pp. 397-405 ◽  
Author(s):  
Wen‐Jyi Hwang ◽  
Chien‐Min Ou ◽  
Ying‐Nan Shih ◽  
Chia‐Tien Dan Lo
Keyword(s):  
Intrusion Detection ◽  
High Throughput ◽  
Network Intrusion Detection ◽  
Low Area ◽  
Network Intrusion

Hybrid Network Intrusion Detection System for Smart Environments Based on Internet of Things

2019 ◽  
Author(s):  
Venkatraman Subbarayalu ◽  
B Surendiran ◽  
P Arun Raj Kumar
Keyword(s):  
Internet Of Things ◽  
Intrusion Detection ◽  
Denial Of Service ◽  
Hybrid Network ◽  
Network Intrusion Detection ◽  
Smart Device ◽  
Smart Environments ◽  
Detection Accuracy ◽  
Network Intrusion ◽  
Iot Devices

Abstract The proliferation of Internet of Things (IoT) devices has led to many applications, including smart homes, smart cities and smart industrial control systems. Attacks like Distributed Denial of Service, event control hijacking, spoofing, event replay and zero day attacks are prevalent in smart environments. Conventional Network Intrusion Detection Systems (NIDSs) are tedious to deploy in the smart environment because of numerous communication architectures, manufacturer policies, technologies, standards and application-specific services. To overcome these challenges, we modeled the operational behavior of IoT network events using timed ACs and proposed a novel hybrid NIDS in this paper. A web server is integrated with IoT devices for remote access, and Constrained Application Protocol is employed in inter- and intra-smart device communication. Experiments are conducted in real time to validate our proposal and achieve 99.17% detection accuracy and 0.01% false positives.

A Studying on Implementation of NIDS Pattern Matching Based on FPGA

2011 ◽  
Vol 403-408 ◽  
pp. 1985-1988
Author(s):  
Jing Jiao Li ◽  
Ho Cholman ◽  
Yong Chen ◽  
Song Ho Pak
Keyword(s):  
Intrusion Detection ◽  
Pattern Matching ◽  
High Throughput ◽  
High Performance ◽  
Low Cost ◽  
Network Intrusion Detection ◽  
Application Area ◽  
Network Intrusion ◽  
Rule Set ◽  
Matching Performance

Intrusion detection for network security is an application area demanding high throughput. The pattern matching in intrusion detection requires extremely high performance to process string matching. Most of pattern matching using software has many time complexities and cannot reach the requirements of high throughput. The pattern matching using hardware considerably improves the speed of matching and has several other advantages. This paper describes a FPGA-based pattern matching architecture, using hashing method called XOR Hashing. The proposed method updates new patterns without reconfiguration and processes the collision and has high matching performance. The proposed system implements the pattern matching by using Snort rule-set, an open source Network Intrusion Detection and has simulation processing on PC. Compared with existing hardware method, the results explained that our method has relatively high performance for the pattern matching and can else process the pattern matching with high performance on low–cost FPGA device.

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