Formal Verification of UML State Machine Diagrams Using Petri Nets

2019 ◽  
pp. 67-74
Author(s):  
Achraf Lyazidi ◽  
Salma Mouline
Keyword(s):  
Petri Nets ◽  
Formal Verification ◽  
State Machine

scholarly journals An Approach for Synthesizing Intelligible State Machine Models from Choreography Using Petri Nets

2014 ◽  
Vol E97.D (5) ◽  
pp. 1171-1180 ◽  
Author(s):  
Toshiyuki MIYAMOTO ◽  
Yasuwo HASEGAWA ◽  
Hiroyuki OIMURA
Keyword(s):  
Petri Nets ◽  
State Machine

Specification and Formal Verification of Safety Properties in Point Automation System by Using Timed-Arc Petri Nets

2014 ◽  
Vol 47 (3) ◽  
pp. 12140-12145 ◽  
Author(s):  
İbrahim ŞENER ◽  
Özgür Turay KAYMAKCI ◽  
İlker ÜSTOĞLU ◽  
Galip CANSEVER
Keyword(s):  
Petri Nets ◽  
Formal Verification ◽  
Automation System ◽  
Safety Properties

Synthesis of Macro Petri Nets into FPGA with Distributed Memories

2012 ◽  
Vol 58 (4) ◽  
pp. 403-410 ◽  
Author(s):  
Arkadiusz Bukowiec ◽  
Marian Adamski
Keyword(s):  
Petri Nets ◽  
Petri Net ◽  
Parallel Implementation ◽  
State Machine ◽  
Logic Circuit ◽  
Digital System ◽  
Decomposition Process ◽  
New Method ◽  
Combinational Circuit ◽  
Distributed Memories

Abstract In this paper a new method of Petri net array-based synthesis is proposed. The method is based on decomposition of colored interpreted macro Petri net into state machine subnets. Each state machine subnet is determined by one color. During the decomposition process macroplaces are expanded or replaced by doublers of macroplace. Such decomposition leads to parallel implementation of a digital system. The structured encoding of places is done by using minimal numbers of bits. Colored microoperations, which are assigned to places, are written into distributed and flexible memories. It leads to realization of a logic circuit in a two-level concurrent structure, where the combinational circuit of the first level is responsible for firing transitions, and the second level memories are used for generation of microoperations. Such an approach allows balanced usage of different kinds of resources available in modern FPGAs

Formal verification of complex business processes based on high-level Petri nets

2017 ◽  
Vol 385-386 ◽  
pp. 39-54 ◽  
Author(s):  
Ahmed Kheldoun ◽  
Kamel Barkaoui ◽  
Malika Ioualalen
Keyword(s):  
Petri Nets ◽  
Formal Verification ◽  
Business Processes ◽  
High Level

5.4.3 Usability of formal verification on EFFBD models: Applying Petri nets to Systems Engineering issues

2007 ◽  
Vol 17 (1) ◽  
pp. 848-859 ◽  
Author(s):  
Charlotte Seidner ◽  
Jean-Philippe Lerat ◽  
Olivier H. Roux
Keyword(s):  
Petri Nets ◽  
Formal Verification ◽  
Systems Engineering

Automatic Formal Verification of SysML State Machine Diagrams for Vehicular Control Systems

2021 ◽  
Author(s):  
Maziar Mahani ◽  
Denise Rizzo ◽  
Chris Paredis ◽  
Yue Wang
Keyword(s):  
Formal Verification ◽  
Control Systems ◽  
State Machine

On Improving Model Checking of Time Petri Nets and Its Application to the Formal Verification

2021 ◽  
Vol 12 (4) ◽  
pp. 68-84
Author(s):  
Naima Jbeli ◽  
Zohra Sbai
Keyword(s):  
Model Checking ◽  
Petri Nets ◽  
Formal Verification ◽  
State Space ◽  
Order Reduction ◽  
The State ◽  
Timing Constraints ◽  
Time Petri Nets ◽  
Explicit Timing ◽  
Class Graph

Time Petri nets (TPN) are successfully used in the specification and analysis of distributed systems that involve explicit timing constraints. Especially, model checking TPN is a hopeful method for the formal verification of such complex systems. For this, it is promising to lean to the construction of an optimized version of the state space. The well-known methods of state space abstraction are SCG (state class graph) and ZBG (graph based on zones). For ZBG, a symbolic state represents the real evaluations of the clocks of the TPN; it is thus possible to directly check quantitative time properties. However, this method suffers from the state space explosion. To attenuate this problem, the authors propose in this paper to combine the ZBG approach with the partial order reduction technique based on stubborn set, leading thus to the proposal of a new state space abstraction called reduced zone-based graph (RZBG). The authors show via case studies the efficiency of the RZBG which is implemented and integrated within the 〖TPN-TCTL〗_h^∆ model checking in the model checker Romeo.

Formal Verification of a Subset of UML Diagrams

2011 ◽  
pp. 14-24
Author(s):  
Allaoua Chaoui ◽  
Okba Tibermacine ◽  
Amer R. Zerek
Keyword(s):  
Formal Verification ◽  
Programming Language ◽  
Formal Specification ◽  
State Machine ◽  
Declarative Programming ◽  
Sequence Diagrams ◽  
Uml Diagrams ◽  
Approach Goals ◽  
Formal Specification Language ◽  
State Machine Diagram

We introduce an approach that deals with the verification of UML collaboration and sequence diagrams in respect to the objects internal behaviors which are commonly represented by state machine diagrams. The approach is based on the translation of theses diagrams to Maude specifications. In fact, Maude is a declarative programming language, an executable formal specification language, and also a formal verification system, which permit the achievement of the approach goals. We define in details the rules of translating UML diagrams elements into their corresponding Maude specifications. We present the algebraic structures that represent the OR-States and the AND-states in a state machine diagram, and the structure that represents the collaboration and the sequence diagrams. Also, we explain the mechanism of the execution and the verification of the translated specification, which is based on rewriting logics rules.

Formal Verification of Distributed Master-Slave Finite State Machine

2021 ◽  
Author(s):  
Marko Popovic ◽  
Vladimir Marinkovic ◽  
Miodrag Djukic ◽  
Miroslav Popovic
Keyword(s):  
Formal Verification ◽  
Finite State Machine ◽  
State Machine ◽  
Finite State
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