scholarly journals One Step in-Memory Solution of Inverse Algebraic Problems

2021 ◽  
pp. 63-76
Author(s):  
Giacomo Pedretti
Keyword(s):  
Memory Device ◽  
Maximum Speed ◽  
Algebraic Operation ◽  
Processing Unit ◽  
Von Neumann ◽  
One Step ◽  
Irregular Data ◽  
Von Neumann Architecture ◽  
Time And Energy ◽  
Inverse Operation

AbstractMachine learning requires to process large amount of irregular data and extract meaningful information. Von-Neumann architecture is being challenged by such computation, in fact a physical separation between memory and processing unit limits the maximum speed in analyzing lots of data and the majority of time and energy are spent to make information travel from memory to the processor and back. In-memory computing executes operations directly within the memory without any information travelling. In particular, thanks to emerging memory technologies such as memristors, it is possible to program arbitrary real numbers directly in a single memory device in an analog fashion and at the array level, execute algebraic operation in-memory and in one step. In this chapter the latest results in accelerating inverse operation, such as the solution of linear systems, in-memory and in a single computational cycle will be presented.

scholarly journals A 0.94 μW 611 KHz In-Situ Logic Operation in Embedded DRAM Memory Arrays in 90 nm CMOS

Electronics ◽  
2019 ◽  
Vol 8 (8) ◽  
pp. 865
Author(s):  
Myeong-Eun Hwang ◽  
Sungoh Kwon
Keyword(s):  
Reducing Power ◽  
Data Traffic ◽  
Von Neumann ◽  
Memory Array ◽  
Process Measurement ◽  
Measurement Results ◽  
Logic Operations ◽  
Von Neumann Architecture ◽  
Time And Energy

Conventional computers based on the Von Neumann architecture conduct computation with repeated data movements between their separate processing and memory units, where each movement takes time and energy. Unlike this approach, we experimentally study memory that can perform computation as well as store data within a generic memory array in a non-Von Neumann architecture way. Memory array can innately perform NOR operation that is functionally complete and thus realize any Boolean functions like inversion (NOT), disjunction (OR) and conjunction (AND) operations. With theoretical exploration of memory array performing Boolean computation along with storing data, we demonstrate another potential of memory array with a test chip fabricated in a 90 nm logic process. Measurement results confirm valid in-situ memory logic operations in a 32-kbit memory system that successfully operates down to 135 mV consuming 130 nW at 750 Hz, reducing power and data traffic between the units by five orders of magnitude at the sacrifice of performance.

scholarly journals Memcomputing NP-complete problems in polynomial time using polynomial resources and collective states

2015 ◽  
Vol 1 (6) ◽  
pp. e1500031 ◽  
Author(s):  
Fabio Lorenzo Traversa ◽  
Chiara Ramella ◽  
Fabrizio Bonani ◽  
Massimiliano Di Ventra
Keyword(s):  
Polynomial Time ◽  
Error Correcting Codes ◽  
Collective State ◽  
Memory Cells ◽  
Computational Power ◽  
Von Neumann ◽  
Complete Problems ◽  
Input Size ◽  
One Step ◽  
Von Neumann Architecture

Memcomputing is a novel non-Turing paradigm of computation that uses interacting memory cells (memprocessors for short) to store and process information on the same physical platform. It was recently proven mathematically that memcomputing machines have the same computational power of nondeterministic Turing machines. Therefore, they can solve NP-complete problems in polynomial time and, using the appropriate architecture, with resources that only grow polynomially with the input size. The reason for this computational power stems from properties inspired by the brain and shared by any universal memcomputing machine, in particular intrinsic parallelism and information overhead, namely, the capability of compressing information in the collective state of the memprocessor network. We show an experimental demonstration of an actual memcomputing architecture that solves the NP-complete version of the subset sum problem in only one step and is composed of a number of memprocessors that scales linearly with the size of the problem. We have fabricated this architecture using standard microelectronic technology so that it can be easily realized in any laboratory setting. Although the particular machine presented here is eventually limited by noise—and will thus require error-correcting codes to scale to an arbitrary number of memprocessors—it represents the first proof of concept of a machine capable of working with the collective state of interacting memory cells, unlike the present-day single-state machines built using the von Neumann architecture.

scholarly journals REGION GROWING IMAGE SEGMENTATION ON LARGE DATASETS USING GPU

2016 ◽  
Vol 15 (14) ◽  
pp. 7486-7497
Author(s):  
Gurpreet Kaur ◽  
Sonika Jindal
Keyword(s):  
Image Segmentation ◽  
Traffic Control ◽  
Cluster Computing ◽  
Region Growing ◽  
Large Data ◽  
Maximum Speed ◽  
Processing Unit ◽  
Small Areas ◽  
Best Fitting ◽  
Seed Pixel

Image segmentation is an important image processing, and it seems everywhere if we want to analyze what inside the image. There are varieties of applications of image segmentation such as the field of filtering noise from image, medical imaging, and locating objects in satellite images and in automatic traffic control systems, machine vision in problem of feature extraction and in recognition. This paper focuses on accelerating the image segmentation mechanism using region growing algorithm inside GPU (Graphical Processing Unit). In region growing algorithm, an initial set of small areas are iteratively merged according to similarity constraints. We have started by choosing an arbitrary seed pixel and compare it with neighboring pixels. Region is grown from the seed pixel by adding in neighboring pixels that are similar, increasing the size of the region. When the growth of one region stops we simply choose another seed pixel which does not yet belong to any region and start again. This whole process is continued until all pixels belong to some region. If any of the segment makers has the fusion cost lower than the maximum fusion cost (a given threshold), it is selected to grow. Avoid information overlapping like two threads attempting to merge its segment with the same adjacent segment.  Experiments have demonstrated that the proposed shape features do not imply in a significant change of the segmentation results, as long as the algorithm’s parameters are properly adjusted. Moreover, experiments for performance evaluation indicated the potential of using GPUs to accelerate this kind of application. For a simple hardware (GeForce 630M GT), the parallel algorithm reached a maximum speed up of approximately 20-30% for different datasets. Considering that segmentation is responsible for a significant portion of the execution time in many image analysis applications, especially in object-oriented analysis of remote sensing images, the experimentally observed acceleration values are significant. Two variants of PBF (Parallel Best Fitting) and PLMBF (Parallel Local Mutual Best Fitting) have been used to analyze the best merging cost of the two segments. It has been found that the PLMBF has been performed better than PBF.  It should also be noted that these performance gains can be obtained with low investment in hardware, as GPUs with increasing processing power are currently available on the market at declining prices. The parallel computational scheme is well suited for cluster computing, leading to a good solution for segmenting very large data sets.

From von Neumann Architecture and Atanasoff’s ABC to Neuromorphic Computation and Kasabov’s NeuCube. Part II: Applications

2018 ◽  
pp. 17-36 ◽  
Author(s):  
Maryam Gholami Doborjeh ◽  
Zohreh Gholami Doborjeh ◽  
Akshay Raj Gollahalli ◽  
Kaushalya Kumarasinghe ◽  
Vivienne Breen ◽  
...  
Keyword(s):  
Von Neumann ◽  
Von Neumann Architecture

The First Generation of Computers

2019 ◽  
pp. 117-142
Author(s):  
Giuseppe Primiero
Keyword(s):  
First Generation ◽  
Point Of View ◽  
Historical Evolution ◽  
Universal Model ◽  
Von Neumann ◽  
Model Of Computation ◽  
Von Neumann Architecture

This chapter starts with the analysis of the engineering foundation of computing which, proceeding in parallelwith themathematical foundation, led to the design and creation of physical computingmachines. It illustrates the historical evolution of the first generation of computing and their technical foundation, known as the von Neumann architecture. Fromthe conceptual point of view, the chapter clarifies the relation between the universal model of computation and the construction of an all-purpose machine.

scholarly journals Implementing the Quantum von Neumann Architecture with Superconducting Circuits

Science ◽  
2011 ◽  
Vol 334 (6052) ◽  
pp. 61-65 ◽  
Author(s):  
M. Mariantoni ◽  
H. Wang ◽  
T. Yamamoto ◽  
M. Neeley ◽  
R. C. Bialczak ◽  
...  
Keyword(s):  
Von Neumann ◽  
Superconducting Circuits ◽  
Von Neumann Architecture

The archive and the processor: The internal logic of Web 2.0

2011 ◽  
Vol 13 (8) ◽  
pp. 1228-1244 ◽  
Author(s):  
Robert W. Gehl
Keyword(s):  
Intellectual Property ◽  
Web 2.0 ◽  
Business Model ◽  
Digital Content ◽  
Affective Processing ◽  
Von Neumann ◽  
Internal Logic ◽  
For Profit ◽  
Von Neumann Architecture ◽  
The Web

In Web 2.0, there is a social dichotomy at work based upon and reflecting the underlying Von Neumann Architecture of computers. In the hegemonic Web 2.0 business model, users are encouraged to process digital ephemera by sharing content, making connections, ranking cultural artifacts, and producing digital content, a mode of computing I call ‘affective processing.’ The Web 2.0 business model imagines users to be a potential superprocessor. In contrast, the memory possibilities of computers are typically commanded by Web 2.0 site owners. They seek to surveil every user action, store the resulting data, protect that data via intellectual property, and mine it for profit. Users are less likely to wield control over these archives. These archives are comprised of the products of affective processing; they are archives of affect, sites of decontextualized data which can be rearranged by the site owners to construct knowledge about Web 2.0 users.

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